swh:1:snp:32555a3fd8878f019c2ebd6c964bc1edcaeff337
Revision 6c7b03e1aef2e92176435f4fa562cc483422d20f authored by Boris Brezillon on 27 March 2015, 22:53:15 UTC, committed by Boris Brezillon on 19 June 2015, 12:43:39 UTC
The PLL impose a certain input range to work correctly, but it appears that
this input range does not apply on the input clock (or parent clock) but
on the input clock after it has passed the PLL divisor.
Fix the implementation accordingly.

Cc: <stable@vger.kernel.org> # v3.14+
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: Jonas Andersson <jonas@microbit.se>
1 parent 03bc10a
History
Tip revision: ffb4d94b4314655cea60ab7962756e6bab72fc7e authored by Linus Torvalds on 30 September 2022, 23:25:52 UTC
Merge tag 'drm-fixes-2022-10-01' of git://anongit.freedesktop.org/drm/drm
Tip revision: ffb4d94
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