Revision 71556b9800fff8bf59075d2c1622acc9d99113ef authored by Linus Torvalds on 16 January 2009, 20:40:37 UTC, committed by Linus Torvalds on 16 January 2009, 20:40:37 UTC
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: (23 commits)
  ACPI PCI hotplug: harden against panic regression
  ACPI: rename main.c to sleep.c
  dell-laptop: move to drivers/platform/x86/ from drivers/misc/
  eeepc-laptop: enable Bluetooth ACPI details
  ACPI: fix ACPI_FADT_S4_RTC_WAKE comment
  kprobes: check CONFIG_FREEZER instead of CONFIG_PM
  PM: Fix freezer compilation if PM_SLEEP is unset
  thermal fixup for broken BIOS which has invalid trip points.
  ACPI: EC: Don't trust ECDT tables from ASUS
  ACPI: EC: Limit workaround for ASUS notebooks even more
  ACPI: thinkpad-acpi: bump up version to 0.22
  ACPI: thinkpad-acpi: handle HKEY event 6030
  ACPI: thinkpad-acpi: clean-up fan subdriver quirk
  ACPI: thinkpad-acpi: start the event hunt season
  ACPI: thinkpad-acpi: handle HKEY thermal and battery alarms
  ACPI: thinkpad-acpi: clean up hotkey_notify()
  ACPI: thinkpad-acpi: use killable instead of interruptible mutexes
  ACPI: thinkpad-acpi: add UWB radio support
  ACPI: thinkpad-acpi: preserve radio state across shutdown
  ACPI: thinkpad-acpi: resume with radios disabled
  ...
2 parent s abcea85 + d45e085
Raw File
DMA-attributes.txt
			DMA attributes
			==============

This document describes the semantics of the DMA attributes that are
defined in linux/dma-attrs.h.

DMA_ATTR_WRITE_BARRIER
----------------------

DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA.  DMA
to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces
all pending DMA writes to complete, and thus provides a mechanism to
strictly order DMA from a device across all intervening busses and
bridges.  This barrier is not specific to a particular type of
interconnect, it applies to the system as a whole, and so its
implementation must account for the idiosyncracies of the system all
the way from the DMA device to memory.

As an example of a situation where DMA_ATTR_WRITE_BARRIER would be
useful, suppose that a device does a DMA write to indicate that data is
ready and available in memory.  The DMA of the "completion indication"
could race with data DMA.  Mapping the memory used for completion
indications with DMA_ATTR_WRITE_BARRIER would prevent the race.

DMA_ATTR_WEAK_ORDERING
----------------------

DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
may be weakly ordered, that is that reads and writes may pass each other.

Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
those that do not will simply ignore the attribute and exhibit default
behavior.
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