https://github.com/torvalds/linux
Revision 7934d69abfa98392433c03136025b71972851733 authored by Sudeep Holla on 21 January 2015, 12:02:30 UTC, committed by Arnd Bergmann on 25 February 2015, 16:12:21 UTC
Commit 5d425c18653731af6 ("arm64: kernel: add support for cpu cache
information") adds cacheinfo support for ARM64. Since there's no
architectural way of detecting the cpus that share particular cache,
device tree can be used and the core cacheinfo already supports the
same.

This patch adds the L2 cache topology on Juno board, FVP/RTSM and
foundation models.

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1 parent c517d83
History
Tip revision: 7934d69abfa98392433c03136025b71972851733 authored by Sudeep Holla on 21 January 2015, 12:02:30 UTC
arm64: Add L2 cache topology to ARM Ltd boards/models
Tip revision: 7934d69
File Mode Size
Documentation
arch
block
crypto
drivers
firmware
fs
include
init
ipc
kernel
lib
mm
net
samples
scripts
security
sound
tools
usr
virt
.gitignore -rw-r--r-- 1.2 KB
.mailmap -rw-r--r-- 4.9 KB
COPYING -rw-r--r-- 18.3 KB
CREDITS -rw-r--r-- 94.0 KB
Kbuild -rw-r--r-- 2.1 KB
Kconfig -rw-r--r-- 252 bytes
MAINTAINERS -rw-r--r-- 298.0 KB
Makefile -rw-r--r-- 53.3 KB
README -rw-r--r-- 18.3 KB
REPORTING-BUGS -rw-r--r-- 7.3 KB

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