https://github.com/torvalds/linux
Revision 7a3136666bc0f0419f7aaa7b1fabb4b0e0a7fb76 authored by Kees Cook on 07 July 2011, 01:10:34 UTC, committed by H. Peter Anvin on 07 July 2011, 03:09:34 UTC
Some BIOSes will reset the Intel MISC_ENABLE MSR (specifically the XD_DISABLE bit) when resuming from S3, which can interact poorly with ebba638ae723d8a8fc2f7abce5ec18b688b791d7. In 32bit PAE mode, this can lead to a fault when EFER is restored by the kernel wakeup routines, due to it setting the NX bit for a CPU that (thanks to the BIOS reset) now incorrectly thinks it lacks the NX feature. (64bit is not affected because it uses a common CPU bring-up that specifically handles the XD_DISABLE bit.) The need for MISC_ENABLE being restored so early is specific to the S3 resume path. Normally, MISC_ENABLE is saved in save_processor_state(), but this happens after the resume header is created, so just reproduce the logic here. (acpi_suspend_lowlevel() creates the header, calls do_suspend_lowlevel, which calls save_processor_state(), so the saved processor context isn't available during resume header creation.) [ hpa: Consider for stable if OK in mainline ] Signed-off-by: Kees Cook <kees.cook@canonical.com> Link: http://lkml.kernel.org/r/20110707011034.GA8523@outflux.net Signed-off-by: H. Peter Anvin <hpa@zytor.com> Cc: Rafael J. Wysocki <rjw@sisk.pl> Cc: <stable@kernel.org> 2.6.38+
1 parent b49c78d
Tip revision: 7a3136666bc0f0419f7aaa7b1fabb4b0e0a7fb76 authored by Kees Cook on 07 July 2011, 01:10:34 UTC
x86, suspend: Restore MISC_ENABLE MSR in realmode wakeup
x86, suspend: Restore MISC_ENABLE MSR in realmode wakeup
Tip revision: 7a31366
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