Revision 7e3297dc280f88ec0c6619a895f3d449776f952e authored by Thomas Bogendoerfer on 27 June 2008, 21:52:26 UTC, committed by Ralf Baechle on 03 July 2008, 18:14:27 UTC
The introduction of a real dma cache invalidate makes it important to have a correct cache line size, otherwise the kernel will gives out two memory segment, which might share one cache line. The R4400 Indy/Indigo2 CPU modules are using a second level cache line size of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for IP22. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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File | Mode | Size |
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Documentation | ||
arch | ||
block | ||
crypto | ||
drivers | ||
fs | ||
include | ||
init | ||
ipc | ||
kernel | ||
lib | ||
mm | ||
net | ||
samples | ||
scripts | ||
security | ||
sound | ||
usr | ||
virt | ||
.gitignore | -rw-r--r-- | 867 bytes |
.mailmap | -rw-r--r-- | 3.6 KB |
COPYING | -rw-r--r-- | 18.3 KB |
CREDITS | -rw-r--r-- | 90.5 KB |
Kbuild | -rw-r--r-- | 2.4 KB |
MAINTAINERS | -rw-r--r-- | 98.3 KB |
Makefile | -rw-r--r-- | 53.8 KB |
README | -rw-r--r-- | 16.5 KB |
REPORTING-BUGS | -rw-r--r-- | 3.1 KB |
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