swh:1:snp:49cd9498d6cccc5e78252c27dcb645bcf7bf0c91
Revision 7e3297dc280f88ec0c6619a895f3d449776f952e authored by Thomas Bogendoerfer on 27 June 2008, 21:52:26 UTC, committed by Ralf Baechle on 03 July 2008, 18:14:27 UTC
The introduction of a real dma cache invalidate makes it important
to have a correct cache line size, otherwise the kernel will gives
out two memory segment, which might share one cache line. The R4400
Indy/Indigo2 CPU modules are using a second level cache line size
of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for
IP22.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1 parent 1faf7f2
History
Tip revision: 644e9524388a5dbc6d4f58c492ee9ef7bd4ddf4d authored by Linus Torvalds on 26 November 2022, 02:02:49 UTC
Merge tag 'for-v6.1-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
Tip revision: 644e952
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