Revision 7f0801e566cc78315e5dc383bf3c3b5b5b436048 authored by Damien Lespiau on 05 February 2015, 19:35:13 UTC, committed by Jani Nikula on 18 March 2015, 08:09:05 UTC
We don't want to end up in a state where we track that the pipe has its primary plane enabled when primary plane registers are programmed with values that look possible but the plane actually disabled. Refuse to read out the fb state when the primary plane isn't enabled. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reported-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Reported-by: Steven Rostedt <rostedt@goodmis.org> Reference: http://mid.gmane.org/20150203191507.GA2374@crion86 Tested-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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nuc900fb.h
/*
*
* Copyright (c) 2009 Nuvoton technology corporation
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Author:
* Wang Qiang(rurality.linux@gmail.com) 2009/12/16
*/
#ifndef __NUC900FB_H
#define __NUC900FB_H
#include <mach/map.h>
#include <linux/platform_data/video-nuc900fb.h>
enum nuc900_lcddrv_type {
LCDDRV_NUC910,
LCDDRV_NUC930,
LCDDRV_NUC932,
LCDDRV_NUC950,
LCDDRV_NUC960,
};
#define PALETTE_BUFFER_SIZE 256
#define PALETTE_BUFF_CLEAR (0x80000000) /* entry is clear/invalid */
struct nuc900fb_info {
struct device *dev;
struct clk *clk;
struct resource *mem;
void __iomem *io;
void __iomem *irq_base;
int drv_type;
struct nuc900fb_hw regs;
unsigned long clk_rate;
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
#endif
/* keep these registers in case we need to re-write palette */
u32 palette_buffer[PALETTE_BUFFER_SIZE];
u32 pseudo_pal[16];
};
int nuc900fb_init(void);
#endif /* __NUC900FB_H */
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