80fa40a | Florian Fainelli | 19 April 2016, 22:35:39 UTC | MIPS: BMIPS: Adjust mips-hpt-frequency for BCM7435 The CPU actually runs at 1405Mhz which gives us a 175625000 Hz MIPS timer frequency (CPU frequency / 8). Fixes: e4c7d009654a ("MIPS: BMIPS: Add BCM7435 dtsi") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jaedon.shin@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/13132/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 15:44:53 UTC |
86ce9a3 | Sashka Nochkin | 20 April 2016, 03:44:45 UTC | mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type Mediatek MT7620 SoC has syscfg0 bits where it sets the type of memory being used. However, sometimes those bits are not set properly (reading "11"). In this case, the SoC assumes SDRAM. The patch below reflects that. Signed-off-by: Sashka Nochkin <linux-mips@durdom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13135/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:39:43 UTC |
6533af4 | Paul Burton | 21 April 2016, 17:04:53 UTC | MIPS: Prevent "restoration" of MSA context in non-MSA kernels If a kernel doesn't support MSA context (ie. CONFIG_CPU_HAS_MSA=n) then it will only keep 64 bits per FP register in thread context, and the calls to set_fpr64 in restore_msa_extcontext will overrun the end of the FP register context into the FCSR & MSACSR values. GCC 6.x has become smart enough to detect this & complain like so: arch/mips/kernel/signal.c: In function 'protected_restore_fp_context': ./arch/mips/include/asm/processor.h:114:17: error: array subscript is above array bounds [-Werror=array-bounds] fpr->val##width[FPR_IDX(width, idx)] = val; \ ~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~ ./arch/mips/include/asm/processor.h:118:1: note: in expansion of macro 'BUILD_FPR_ACCESS' BUILD_FPR_ACCESS(64) The only way to trigger this code to run would be for a program to set up an artificial extended MSA context structure following a sigframe & execute sigreturn. Whilst this doesn't allow a program to write to any state that it couldn't already, it makes little sense to allow this "restoration" of MSA context in a system that doesn't support MSA. Fix this by killing a program with SIGSYS if it tries something as crazy as "restoring" fake MSA context in this way, also fixing the build error & allowing for most of restore_msa_extcontext to be optimised out of kernels without support for MSA. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reported-by: Michal Toman <michal.toman@imgtec.com> Fixes: bf82cb30c7e5 ("MIPS: Save MSA extended context around signals") Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: James Hogan <james.hogan@imgtec.com> Cc: Michal Toman <michal.toman@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable <stable@vger.kernel.org> # v4.3+ Patchwork: https://patchwork.linux-mips.org/patch/13164/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:35:57 UTC |
1fa4055 | James Hogan | 22 April 2016, 17:19:17 UTC | MIPS: cevt-r4k: Dynamically calculate min_delta_ns Calculate the MIPS clockevent device's min_delta_ns dynamically based on the time it takes to perform the mips_next_event() sequence. Virtualisation in particular makes the current fixed min_delta of 0x300 inappropriate under some circumstances, as the CP0_Count and CP0_Compare registers may be being emulated by the hypervisor, and the frequency may not correspond directly to the CPU frequency. We actually use twice the median of multiple 75th percentiles of multiple measurements of how long the mips_next_event() sequence takes, in order to fairly efficiently eliminate outliers due to unexpected hypervisor latency (which would need handling with retries when it occurs during normal operation anyway). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13176/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
24e1df6 | James Hogan | 22 April 2016, 17:19:15 UTC | MIPS: malta-time: Take seconds into account When estimating the clock frequency based on the RTC, take seconds into account in case the Update In Progress (UIP) bit wasn't seen. This can happen in virtual machines (which may get pre-empted by the hypervisor at inopportune times) with QEMU emulating the RTC (and in fact not setting the UIP bit for very long), especially on slow hosts such as FPGA systems and hardware emulators. This results in several seconds actually having elapsed before seeing the UIP bit instead of just one second, and exaggerated timer frequencies. While updating the comments, they're also fixed to match the code in that the rising edge of the update flag is detected first, not the falling edge. The rising edge gives a more precise point to read the counters in a virtualised system than the falling edge, resulting in a more accurate frequency. It does however mean that we have to also wait for the falling edge before doing the read of the RTC seconds register, otherwise it seems to be possible in slow hardware emulation to stray into the interval when the RTC time is undefined during the update (at least 244uS after the rising edge of the update flag). This can result in both seconds values reading the same, and it wrapping to 60 seconds, vastly underestimating the frequency. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13174/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
aab4673 | James Hogan | 22 April 2016, 17:19:14 UTC | MIPS: malta-time: Start GIC count before syncing to RTC The sampling of the GIC counter on Malta after observing a rising edge of the RTC update flag differs slightly between the first and second sample, with the first sample also calling gic_start_count(). The two samples should really be taken as similarly as possible to get the most accurate figure, so move the gic_start_count() call before detecting the rising edge. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13173/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
6b83225 | Paul Burton | 21 April 2016, 11:43:58 UTC | MIPS: Force CPUs to lose FP context during mode switches Commit 9791554b45a2 ("MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS") added support for the PR_SET_FP_MODE prctl, which allows a userland program to modify its FP mode at runtime. This is most notably required if dynamic linking leads to the FP mode requirement changing at runtime from that indicated in the initial executable's ELF header. In order to avoid overhead in the general FP context restore code, it aimed to have threads in the process become unable to enable the FPU during a mode switch & have the thread calling the prctl syscall wait for all other threads in the process to be context switched at least once. Once that happens we can know that no thread in the process whose mode will be switched has live FP context, and it's safe to perform the mode switch. However in the (rare) case of modeswitches occurring in multithreaded programs this can lead to indeterminate delays for the thread invoking the prctl syscall, and the code monitoring for those context switches was woefully inadequate for all but the simplest cases. Fix this by broadcasting an IPI if other CPUs may have live FP context for an affected thread, with a handler causing those CPUs to relinquish their FPU ownership. Threads will then be allowed to continue running but will stall on the wait_on_atomic_t in enable_restore_fp_context if they attempt to use FP again whilst the mode switch is still in progress. The end result is less fragile poking at scheduler context switch counts & a more expedient completion of the mode switch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Fixes: 9791554b45a2 ("MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS") Reviewed-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: stable <stable@vger.kernel.org> # v4.0+ Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13145/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
bd239f1 | Paul Burton | 21 April 2016, 11:43:57 UTC | MIPS: Disable preemption during prctl(PR_SET_FP_MODE, ...) Whilst a PR_SET_FP_MODE prctl is performed there are decisions made based upon whether the task is executing on the current CPU. This may change if we're preempted, so disable preemption to avoid such changes for the lifetime of the mode switch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Fixes: 9791554b45a2 ("MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS") Reviewed-by: Maciej W. Rozycki <macro@imgtec.com> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: stable <stable@vger.kernel.org> # v4.0+ Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13144/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
e70ac02 | Paul Burton | 21 April 2016, 11:25:38 UTC | MIPS: Allow emulation for unaligned [LS]DXC1 instructions If an address error exception occurs for a LDXC1 or SDXC1 instruction, within the cop1x opcode space, allow it to be passed through to the FPU emulator rather than resulting in a SIGILL. This causes LDXC1 & SDXC1 to be handled in a manner consistent with the more common LDC1 & SDC1 instructions. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13143/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
abf378b | Maciej W. Rozycki | 12 May 2016, 09:19:08 UTC | MIPS: ptrace: Prevent writes to read-only FCSR bits Correct the cases missed with commit 9b26616c8d9d ("MIPS: Respect the ISA level in FCSR handling") and prevent writes to read-only FCSR bits there. This in particular applies to FP context initialisation where any IEEE 754-2008 bits preset by `mips_set_personality_nan' are cleared before the relevant ptrace(2) call takes effect and the PTRACE_POKEUSR request addressing FPC_CSR where no masking of read-only FCSR bits is done. Remove the FCSR clearing from FP context initialisation then and unify PTRACE_POKEUSR/FPC_CSR and PTRACE_SETFPREGS handling, by factoring out code from `ptrace_setfpregs' and calling it from both places. This mostly matters to soft float configurations where the emulator can be switched this way to a mode which should not be accessible and cannot be set with the CTC1 instruction. With hard float configurations any effect is transient anyway as read-only bits will retain their values at the time the FP context is restored. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: stable@vger.kernel.org # v4.0+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13239/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
4249548 | Maciej W. Rozycki | 12 May 2016, 09:18:27 UTC | MIPS: ptrace: Fix FP context restoration FCSR regression Fix a floating-point context restoration regression introduced with commit 9b26616c8d9d ("MIPS: Respect the ISA level in FCSR handling") that causes a Floating Point exception and consequently a kernel oops with hard float configurations when one or more FCSR Enable and their corresponding Cause bits are set both at a time via a ptrace(2) call. To do so reinstate Cause bit masking originally introduced with commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits") to address this exact problem and then inadvertently removed from the PTRACE_SETFPREGS request with the commit referred above. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: stable@vger.kernel.org # v4.0+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13238/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
9125f19 | Purna Chandra Mandal | 13 May 2016, 07:52:41 UTC | MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding - now clock nodes definition is merged with core .dtsi file - only one rootclk is now part of DT - clock clients also updated based on new binding doc Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Sandeep Sheriker <sandeepsheriker.mallikarjun@microchip.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13248/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
ce6e118 | Purna Chandra Mandal | 13 May 2016, 07:52:40 UTC | CLK: microchip: Add Microchip PIC32 clock driver. This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
d863dc9 | Purna Chandra Mandal | 13 May 2016, 07:52:39 UTC | dt/bindings/clk: Add PIC32 clock binding documentation. Document the devicetree bindings for the clock driver found on Microchip PIC32 class devices. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13246/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
c9babb1 | Maciej W. Rozycki | 13 May 2016, 06:21:40 UTC | MIPS: ELF: Unify ABI classification macros Remove a duplicate o32 `elf_check_arch' implementation, move all macro variants to <asm/elf.h> and define them unconditionally under indvidual names, substituting alias `elf_check_arch' definitions in variant code. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13245/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
4a60ad5 | Maciej W. Rozycki | 13 May 2016, 06:20:55 UTC | MIPS: ELF: Unify __MIPS_O32_FP64_MUST_BE_ZERO definitions Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13244/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
de70416 | Maciej W. Rozycki | 13 May 2016, 06:20:16 UTC | MIPS: ELF: Deconditionalise ABI flags definitions Move the `mips_elf_abiflags_v0' structure and FP ABI flag macros outside #ifndef ELF_ARCH. These are public interfaces. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13243/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
4b62fad | James Hogan | 11 May 2016, 14:50:32 UTC | MIPS: Print GuestCtl1 on machine check exception The GuestCtl1 CP0 register can contain the GuestID used for root TLB operations, which affects TLB matching. The other TLB registers are already dumped out to the log on a machine check exception due to multiple matching TLB entries, so also dump the value of the GuestCtl1 register if GuestIDs are supported. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13232/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
382208d | James Hogan | 11 May 2016, 14:50:31 UTC | MIPS: dump_tlb: Preserve and dump GuestID The GuestID for root TLB operations (GuestCtl1.RID) is modified by TLB reads, so needs preserving by dump_tlb() like the ASID field of EntryHi. Also dump the GuestID of each entry if it exists alongside the ASID, as it forms an important part of the TLB entry when VZ guests are used. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13230/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
6ad816e | James Hogan | 11 May 2016, 14:50:30 UTC | MIPS: Add probing & defs for VZ & guest features Add a few new cpu-features.h definitions for VZ sub-features, namely the existence of the CP0_GuestCtl0Ext, CP0_GuestCtl1, and CP0_GuestCtl2 registers, and support for GuestID to dialias TLB entries belonging to different guests. Also add certain features present in the guest, with the naming scheme cpu_guest_has_*. These are added separately to the main options bitfield since they generally parallel similar features in the root context. A few of these (FPU, MSA, watchpoints, perf counters, CP0_[X]ContextConfig registers, MAAR registers, and probably others in future) can be dynamically configured in the guest context, for which the cpu_guest_has_dyn_* macros are added. [ralf@linux-mips.org: Resolve merge conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13231/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
7eb9111 | James Hogan | 11 May 2016, 14:50:29 UTC | MIPS: Add guest CP0 accessors Add guest CP0 accessors and guest TLB operations along the same lines as the existing macros and functions for the root CP0. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13229/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
f913e9e | James Hogan | 11 May 2016, 14:50:28 UTC | MIPS: Add register definitions for VZ ASE registers Add various register definitions to <asm/mipsregs.h> for the coprocessor zero registers in the VZ ASE, namely CP0_GuestCtl0, CP0_GuestCtl0Ext, CP0_GuestCtl1, CP0_GuestCtl2, CP0_GuestCtl3, and CP0_GTOffset. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13228/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
9e575f7 | James Hogan | 11 May 2016, 14:50:27 UTC | MIPS: Avoid magic numbers probing kscratch_mask The decode_config4() function reads kscratch_mask from CP0_Config4.KScrExist using a hard coded shift and mask. We already have a definition for the mask in mipsregs.h, so add a definition for the shift and make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13227/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
30228c4 | James Hogan | 11 May 2016, 12:50:53 UTC | MIPS: Add perf counter feature Add CPU feature for standard MIPS r2 performance counters, as determined by the Config1.PC bit. Both perf_events and oprofile probe this bit, so lets combine the probing and change both to use cpu_has_perf. This will also be used for VZ support in KVM to know whether performance counters exist which can be exposed to guests. [ralf@linux-mips.org: resolve conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Robert Richter <rric@kernel.org> Cc: linux-mips@linux-mips.org Cc: oprofile-list@lists.sf.net Patchwork: https://patchwork.linux-mips.org/patch/13226/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
f18bdfa | James Hogan | 11 May 2016, 12:50:52 UTC | MIPS: Add defs & probing of [X]ContextConfig The CP0_[X]ContextConfig registers are present if CP0_Config3.CTXTC or CP0_Config3.SM are set, and provide more control over which bits of CP0_[X]Context are set to the faulting virtual address on a TLB exception. KVM/VZ will need to be able to save and restore these registers in the guest context, so add the relevant definitions and probing of the ContextConfig feature in the root context first. [ralf@linux-mips.org: resolve merge conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13225/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
e06a154 | James Hogan | 11 May 2016, 12:50:51 UTC | MIPS: Add defs & probing of BadInstr[P] registers The optional CP0_BadInstr and CP0_BadInstrP registers are written with the encoding of the instruction that caused a synchronous exception to occur, and the prior branch instruction if in a delay slot. These will be useful for instruction emulation in KVM, and especially for VZ support where reading guest virtual memory is a bit more awkward. Add CPU option numbers and cpu_has_* definitions to indicate the presence of each registers, and add code to probe for them using bits in the CP0_Config3 register. [ralf@linux-mips.org: resolve merge conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13224/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
37fb60f | James Hogan | 11 May 2016, 12:50:50 UTC | MIPS: Add defs & probing of extended CP0_EBase The CP0_EBase register may optionally have a write gate (WG) bit to allow the upper bits to be written, i.e. bits 31:30 on MIPS32 since r3 (to allow for an exception base outside of KSeg0/KSeg1 when segmentation control is in use) and bits 63:30 on MIPS64 (which also implies the extension of CP0_EBase to 64 bits long). The presence of this feature will need to be known about for VZ support in order to correctly save and restore all the bits of the guest CP0_EBase register, so add CPU feature definition and probing for this feature. Probing the WG bit on MIPS64 can be a bit fiddly, since 64-bit COP0 register access instructions were UNDEFINED for 32-bit registers prior to MIPS r6, and it'd be nice to be able to probe without clobbering the existing state, so there are 3 potential paths: - If we do a 32-bit read of CP0_EBase and the WG bit is already set, the register must be 64-bit. - On MIPS r6 we can do a 64-bit read-modify-write to set CP0_EBase.WG, since the upper bits will read 0 and be ignored on write if the register is 32-bit. - On pre-r6 cores, we do a 32-bit read-modify-write of CP0_EBase. This avoids the potentially UNDEFINED behaviour, but will clobber the upper 32-bits of CP0_EBase if it isn't a simple sign extension (which also requires us to ensure BEV=1 or modifying the exception base would be UNDEFINED too). It is hopefully unlikely a bootloader would set up CP0_EBase to a 64-bit segment and leave WG=0. [ralf@linux-mips.org: Resolved merge conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Tested-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13223/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
37af2f3 | James Hogan | 11 May 2016, 12:50:49 UTC | MIPS: Define & use CP0_EBase bit definitions Add definitions for the bits & fields in the CP0_EBase register, and use them from a few different places in arch/mips which hardcoded these values. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Jayachandran C <jchandra@broadcom.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13222/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
dc3ee60 | Stephen Boyd | 20 April 2016, 01:34:37 UTC | MIPS: alchemy: Remove CLK_IS_ROOT This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13134/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
9c938a0 | Stephen Boyd | 20 April 2016, 01:33:21 UTC | MIPS: ath79: Remove CLK_IS_ROOT This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13133/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
8f4703a | Aurelien Jarno | 10 May 2016, 22:50:03 UTC | MIPS: Octeon: detect and fix byte swapped initramfs Octeon machines support running in little endian mode. U-Boot usually runs in big endian-mode. Therefore the initramfs is loaded in big endian mode, and the kernel later tries to access it in little endian mode. This patch fixes that by detecting byte swapped initramfs using either the CPIO header or the header from standard compression methods, and byte swaps it if needed. It first checks that the header doesn't match in the native endianness to avoid false detections. It uses the kernel decompress library so that we don't have to maintain the list of magics if some decompression methods are added to the kernel. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13219/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
b472080 | Florian Fainelli | 09 February 2016, 20:55:53 UTC | MIPS: BMIPS: BMIPS4380 and BMIPS5000 support RIXI Make BMIPS4380 and BMIPS5000 advertise support for RIXI through cpu_probe_broadcom(). bmips_cpu_setup() needs to be called shortly after that, during prom_init() in order to enable the proper Broadcom-specific register to turn on RIXI and the "rotr" instruction. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: pgynther@google.com Cc: paul.burton@imgtec.com Cc: ddaney.cavm@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12507/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
2e27476 | Florian Fainelli | 09 February 2016, 20:55:52 UTC | MIPS: Move RIXI exception enabling after vendor-specific cpu_probe Some processors may not have the RIXI bit advertised in the Config3 register, not being a MIPS32R2 or R6 core, yet, they might be supporting it through a different way, which is overriden during vendor-specific cpu_probe(). Move the RIXI exceptions enabling after the vendor-specific cpu_probe() function has had a change to run and override the current CPU's options with MIPS_CPU_RIXI. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: pgynther@google.com Cc: paul.burton@imgtec.com Cc: ddaney.cavm@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12506/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
8256b17 | Florian Fainelli | 09 February 2016, 20:55:51 UTC | MIPS: Allow RIXI to be used on non-R2 or R6 cores Some processors, like Broadcom's BMIPS4380 and BMIPS5000 support RIXI and the "rotr" instruction, which can be used to get a slightly more efficient page table layout. Introduce a CONFIG_CPU_HAS_RIXI such that those cores can benefit from this feature. Perform the conditional check updates where relevant. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: pgynther@google.com Cc: paul.burton@imgtec.com Cc: ddaney.cavm@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12505/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
e56c7e1 | Paul Burton | 19 April 2016, 08:25:11 UTC | MIPS: mm: Panic if an XPA kernel is run without RIXI XPA kernels hardcode for the presence of RIXI - the PTE format & its handling presume RI & XI bits. Make this dependence explicit by panicing if we run on a system that violates it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13125/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
4b6f99d | James Hogan | 19 April 2016, 08:25:10 UTC | MIPS: mm: Don't do MTHC0 if XPA not present Performing an MTHC0 instruction without XPA being present will trigger a reserved instruction exception, therefore conditionalise the use of this instruction when building TLB handlers (build_update_entries()), and in __update_tlb(). This allows an XPA kernel to run on non XPA hardware without that instruction implemented, just like it can run on XPA capable hardware without XPA in use (with the noxpa kernel argument) or with XPA not configured in hardware. [paul.burton@imgtec.com: - Rebase atop other TLB work. - Add "mm" to subject. - Handle the __kmap_pgprot case.] Fixes: c5b367835cfc ("MIPS: Add support for XPA.") Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: David Hildenbrand <dahi@linux.vnet.ibm.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Jerome Marchand <jmarchan@redhat.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13124/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
2caa89b | Paul Burton | 19 April 2016, 08:25:09 UTC | MIPS: mm: Simplify build_update_entries We can simplify build_update_entries by unifying the code for the 36 bit physical addressing with MIPS32 case with the general case, by using pte_off_ variables in all cases & handling the trivial _PAGE_GLOBAL_SHIFT == 0 case in build_convert_pte_to_entrylo. This leaves XPA as the only special case. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13123/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
b4ebbb8 | Paul Burton | 19 April 2016, 08:25:08 UTC | MIPS: mm: Be more explicit about PTE mode bit handling The XPA case in iPTE_SW or's in software mode bits to the pte_low value (which is what actually ends up in the high 32 bits of EntryLo...). It does this presuming that only bits in the upper 16 bits of the 32 bit pte_low value will be set. Make this assumption explicit with a BUG_ON. A similar assumption is made for the hardware mode bits, which are or'd in with a single ori instruction. Make that assumption explicit with a BUG_ON too. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13122/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
bbeeffe | Paul Burton | 19 April 2016, 08:25:07 UTC | MIPS: mm: Pass scratch register through to iPTE_SW Rather than hardcode a scratch register for the XPA case in iPTE_SW, pass one through from the work registers allocated by the caller. This allows for the XPA path to function correctly regardless of the work registers in use. Without doing this there are cases (where KScratch registers are unavailable) in which iPTE_SW will incorrectly clobber $1 despite it already being in use for the PTE or PTE pointer. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13121/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
f383219 | James Hogan | 19 April 2016, 08:25:06 UTC | MIPS: mm: Don't clobber $1 on XPA TLB refill For XPA kernels build_update_entries() uses $1 (at) as a scratch register, but doesn't arrange for it to be preserved, so it will always be clobbered by the TLB refill exception. Although this register normally has a very short lifetime that doesn't cross memory accesses, TLB refills due to instruction fetches (either on a page boundary or after preemption) could clobber live data, and its easy to reproduce the clobber with a little bit of assembler code. Note that the use of a hardware page table walker will partly mask the problem, as the TLB refill handler will not always be invoked. This is fixed by avoiding the use of the extra scratch register. The pte_high parts (going into the lower half of the EntryLo registers) are loaded and manipulated separately so as to keep the PTE pointer around for the other halves (instead of storing in the scratch register), and the pte_low parts (going into the high half of the EntryLo registers) are masked with 0x00ffffff using an ext instruction (instead of loading 0x00ffffff into the scratch register and AND'ing). [paul.burton@imgtec.com: - Rebase atop other TLB work. - Use ext instead of an sll, srl sequence. - Use cpu_has_xpa instead of #ifdefs. - Modify commit subject to include "mm".] Fixes: c5b367835cfc ("MIPS: Add support for XPA.") Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13120/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
7b2cb64 | Paul Burton | 19 April 2016, 08:25:05 UTC | MIPS: mm: Fix MIPS32 36b physical addressing (alchemy, netlogic) There are 2 distinct cases in which a kernel for a MIPS32 CPU (CONFIG_CPU_MIPS32=y) may use 64 bit physical addresses (CONFIG_PHYS_ADDR_T_64BIT=y): - 36 bit physical addressing as used by RMI Alchemy & Netlogic XLP/XLR CPUs. - MIPS32r5 eXtended Physical Addressing (XPA). These 2 cases are distinct in that they require different behaviour from the kernel - the EntryLo registers have different formats. Until Linux v4.1 we only supported the first case, with code conditional upon the 2 aforementioned Kconfig variables being set. Commit c5b367835cfc ("MIPS: Add support for XPA.") added support for the second case, but did so by modifying the code that existed for the first case rather than treating the 2 cases as distinct. Since the EntryLo registers have different formats this breaks the 36 bit Alchemy/XLP/XLR case. Fix this by splitting the 2 cases, with XPA cases now being conditional upon CONFIG_XPA and the non-XPA case matching the code as it existed prior to commit c5b367835cfc ("MIPS: Add support for XPA."). Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reported-by: Manuel Lauss <manuel.lauss@gmail.com> Tested-by: Manuel Lauss <manuel.lauss@gmail.com> Fixes: c5b367835cfc ("MIPS: Add support for XPA.") Cc: James Hogan <james.hogan@imgtec.com> Cc: David Daney <david.daney@cavium.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: David Hildenbrand <dahi@linux.vnet.ibm.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Ingo Molnar <mingo@kernel.org> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: stable@vger.kernel.org # v4.1+ Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13119/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
745f355 | Paul Burton | 19 April 2016, 08:25:04 UTC | MIPS: mm: Unify pte_page definition The same definition for pte_page is duplicated for the MIPS32 PHYS_ADDR_T_64BIT case & the generic case. Unify them by moving a single definition outside of preprocessor conditionals. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13117/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
780602d | Paul Burton | 19 April 2016, 08:25:03 UTC | MIPS: mm: Standardise on _PAGE_NO_READ, drop _PAGE_READ Ever since support for RI/XI was implemented by commit 6dd9344cfc41 ("MIPS: Implement Read Inhibit/eXecute Inhibit") we've had a mixture of _PAGE_READ & _PAGE_NO_READ bits. Rather than keep both around, switch away from using _PAGE_READ to determine page presence & instead invert the use to _PAGE_NO_READ. Wherever we formerly had no definition for _PAGE_NO_READ, change what was _PAGE_READ to _PAGE_NO_READ. The end result is that we consistently use _PAGE_NO_READ to determine whether a page is readable, regardless of whether RI/XI is implemented. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: David Daney <david.daney@cavium.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13116/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
6949770 | Paul Burton | 19 April 2016, 08:25:02 UTC | MIPS: Use enums to make asm/pgtable-bits.h readable asm/pgtable-bits.h has grown to become an unreadable mess of #ifdef directives defining bits conditionally upon other bits all at the preprocessing stage, for no good reason. Instead of having quite so many #ifdef's, simply use enums to provide sequential numbering for bit shifts, without having to keep track manually of what the last bit defined was. Masks are defined separately, after the shifts, which allows for most of their definitions to be reused for all systems rather than duplicated. This patch is not intended to make any behavioural change to the code - all bits should be used in the same way they were before this patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13115/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
253f0d4 | Paul Burton | 19 April 2016, 08:25:01 UTC | MIPS: Remove redundant asm/pgtable-bits.h inclusions asm/pgtable-bits.h is included in 2 assembly files and thus has to ifdef around C code, however nothing defined by the header is used in either of the assembly files that include it. Remove the redundant inclusions such that asm/pgtable-bits.h doesn't need to #ifdef around C code, for cleanliness and in preparation for later patches which will add more C. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13114/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 13:30:25 UTC |
14bc241 | James Hogan | 19 April 2016, 08:25:00 UTC | MIPS: Fix HTW config on XPA kernel without LPA enabled The hardware page table walker (HTW) configuration is broken on XPA kernels where XPA couldn't be enabled (either nohtw or the hardware doesn't support it). This is because the PWSize.PTEW field (PTE width) was only set to 8 bytes (an extra shift of 1) in config_htw_params() if PageGrain.ELPA (enable large physical addressing) is set. On an XPA kernel though the size of PTEs is fixed at 8 bytes regardless of whether XPA could actually be enabled. Fix the initialisation of this field based on sizeof(pte_t) instead. Fixes: c5b367835cfc ("MIPS: Add support for XPA.") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Steven J. Hill <sjhill@realitydiluted.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13113/ Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:24 UTC |
1282257 | James Hogan | 19 April 2016, 08:24:59 UTC | MIPS: Separate XPA CPU feature into LPA and MVH XPA (eXtended Physical Addressing) should be detected as a combination of two architectural features: - Large Physical Address (as per Config3.LPA). With XPA this will be set on MIPS32r5 cores, but it may also be set for MIPS64r2 cores too. - MTHC0/MFHC0 instructions (as per Config5.MVH). With XPA this will be set, but it may also be set in VZ guest context even when Config3.LPA in the guest context has been cleared by the hypervisor. As such, XPA is only usable if both bits are set. Update CPU features to separate these two features, with cpu_has_xpa requiring both to be set. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13112/ Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:24 UTC |
ab4a92e | Paul Burton | 21 April 2016, 13:04:55 UTC | MIPS: math-emu: Fix jalr emulation when rd == $0 When emulating a jalr instruction with rd == $0, the code in isBranchInstr was incorrectly writing to GPR $0 which should actually always remain zeroed. This would lead to any further instructions emulated which use $0 operating on a bogus value until the task is next context switched, at which point the value of $0 in the task context would be restored to the correct zero by a store in SAVE_SOME. Fix this by not writing to rd if it is $0. Fixes: 102cedc32a6e ("MIPS: microMIPS: Floating point support.") Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: stable <stable@vger.kernel.org> # v3.10 Patchwork: https://patchwork.linux-mips.org/patch/13160/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:24 UTC |
db57f29 | Paul Burton | 21 April 2016, 13:04:54 UTC | MIPS: math-emu: Fix m{add,sub}.s shifts The code in _sp_maddf (formerly ieee754sp_madd) appears to have been copied verbatim from ieee754sp_add, and although it's adding the unpacked "r" & "z" floats it kept using macros that operate on "x" & "y". This led to the addition being carried out incorrectly on some mismash of the product, accumulator & multiplicand fields. Typically this would lead to the assertions "ze == re" & "ze <= SP_EMAX" failing since ze & re hadn't been operated upon. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction") Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13159/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:23 UTC |
5c18c93 | Paul Burton | 21 April 2016, 13:04:53 UTC | MIPS: math-emu: Fix code indentation A line incrementing the re variable was indented a level too deep in ieee754dp_mul, making the code unclear to read. Fix the indentation. This appears to have been copied verbatim along with the rest of the multiplication code to ieee754dp_maddf, now _dp_maddf, too so fix the indentation there too. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13158/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:23 UTC |
95bff24 | Paul Burton | 21 April 2016, 13:04:52 UTC | MIPS: math-emu: Fix bit-width in ieee754dp_{mul, maddf, msubf} comments A comment in ieee754dp_mul indicates that the code is about to perform a 32b x 32b multiplication & keep the high 32b of the result. It appears this was copied from the single-precision multiplication code, since the code actually goes on to perform a 64b x 64b multiplication & keep the high 64b of the result. Fix the comment to indicate 64b. It appears also that this comment was copied verbatim along with the rest of the multiplication code into ieee754dp_maddf, which has since been renamed _dp_maddf. Fix the same issue there. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13157/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:23 UTC |
e2d11e1 | Paul Burton | 21 April 2016, 13:04:51 UTC | MIPS: math-emu: Add z argument macros Introduce macros for handling the "z" argument to maddf & msubf, making its handling consistent with that of the "x" & "y" arguments rather than open-coding equivalents. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13156/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:22 UTC |
d728f67 | Paul Burton | 21 April 2016, 13:04:50 UTC | MIPS: math-emu: Unify ieee754dp_m{add,sub}f The code for emulating MIPSr6 madd.d & msub.d instructions has previously been implemented as 2 different functions, namely ieee754dp_maddf & ieee754dp_msubf. The difference in behaviour of these 2 instructions is merely the sign of the product, so we can easily share the code implementing them. Do this for the double precision variant, removing the original ieee754dp_msubf in favor of reusing the code from ieee754dp_maddf. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13155/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:22 UTC |
6162051 | Paul Burton | 21 April 2016, 13:04:49 UTC | MIPS: math-emu: Unify ieee754sp_m{add,sub}f The code for emulating MIPSr6 madd.s & msub.s instructions has previously been implemented as 2 different functions, namely ieee754sp_maddf & ieee754sp_msubf. The difference in behaviour of these 2 instructions is merely the sign of the product, so we can easily share the code implementing them. Do this for the single precision variant, removing the original ieee754sp_msubf in favor of reusing the code from ieee754sp_maddf. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:22 UTC |
4b820d9 | Paul Burton | 21 April 2016, 13:04:48 UTC | MIPS: math-emu: Emulate MIPSr6 sel.fmt instruction Add support for emulating the MIPSr6 sel.fmt instruction, which was previously missing from the FPU emulation code. This instruction selects its result from 2 possible source registers, based upon bit 0 of the destination register, and is valid only for S (single) & D (double) data types. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13153/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:22 UTC |
b6d5c4e | Paul Burton | 21 April 2016, 13:04:47 UTC | MIPS: inst: Declare fsel_op for sel.fmt instruction Declare the opcode for the MIPSr6 sel.fmt instruction, as fsel_op in order to match other FP op names. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13152/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:21 UTC |
ac14969 | Paul Burton | 21 April 2016, 13:04:46 UTC | MIPS: Fix BC1{EQ,NE}Z return offset calculation The conditions for branching when emulating the BC1EQZ & BC1NEZ instructions were backwards, leading to each of those instructions being treated as the other. Fix this by reversing the conditions, and clear up the code a little for readability & checkpatch. Fixes: c8a34581ec09 ("MIPS: Emulate the BC1{EQ,NE}Z FPU instructions") Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13151/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:21 UTC |
93583e1 | Paul Burton | 21 April 2016, 13:04:45 UTC | MIPS: math-emu: Fix BC1{EQ,NE}Z emulation The conditions for branching when emulating the BC1EQZ & BC1NEZ instructions were backwards, leading to each of those instructions being treated as the other. Fix this by reversing the conditions, and clear up the code a little for readability & checkpatch. Fixes: c909ca718e8f ("MIPS: math-emu: Emulate missing BC1{EQ,NE}Z instructions") Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13150/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:21 UTC |
ed47e15 | Rabin Vincent | 28 April 2016, 09:03:09 UTC | MIPS: Add support for extending builtin cmdline Allow the builtin command line to be extended by what the bootloader passes in. For example, the bootloader can pass specific arguments depending on the boot mode, and these should override the defaults in the builtin cmdline. The default MIPS_CMDLINE_FROM_BOOTLOADER option prepends the bootloader's cmdline to the builtin cmdline so is not suitable for this purpose. Signed-off-by: Rabin Vincent <rabinv@axis.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13181/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:21 UTC |
e54ad8c | Rabin Vincent | 28 April 2016, 09:03:08 UTC | MIPS: Don't add leading spacing to command lines The leading spaces don't affect functionality but are unnecessary. Signed-off-by: Rabin Vincent <rabinv@axis.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13180/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:20 UTC |
105c22c | James Hogan | 29 April 2016, 16:29:29 UTC | MIPS: genex: Indent delay slots & clean whitespace Various branches and jumps in noreorder parts of genex.S don't have their delay slot instructions indented conventionally with the extra space. Fix these, as well as various other inconsistent whitespace problems in this file, such as spaces used after some opcodes instead of a tab. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13196/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:20 UTC |
2db003a | Paul Burton | 06 May 2016, 13:36:24 UTC | MIPS: Support extended ASIDs Add support for extended ASIDs as determined by the Config4.AE bit. Since the only supported CPUs known to implement this are Netlogic XLP and MIPS I6400, select this variable ASID support based upon CONFIG_CPU_XLP and CONFIG_CPU_MIPSR6. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Jayachandran C. <jchandra@broadcom.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13211/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:20 UTC |
4edf00a | Paul Burton | 06 May 2016, 13:36:23 UTC | MIPS: Retrieve ASID masks using function accepting struct cpuinfo_mips In preparation for supporting variable ASID masks, retrieve ASID masks using functions in asm/cpu-info.h which accept struct cpuinfo_mips. This will allow those functions to determine the ASID mask based upon the CPU in a later patch. This also allows for the r3k & r8k cases to be handled in Kconfig, which is arguably cleaner than the previous #ifdefs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13210/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:20 UTC |
f1b711c | James Hogan | 06 May 2016, 13:36:22 UTC | MIPS: KVM/locore.S: Relax noat Now that the at register ($1) is no longer saved by __kvm_mips_vcpu_run(), relax the noat assembler directive so that it only applies around code where at is restored before entering guest, and saved after exiting guest. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13209/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:19 UTC |
1300fcd | James Hogan | 06 May 2016, 13:36:21 UTC | MIPS: KVM/locore.S: Only preserve callee saved registers Update __kvm_mips_vcpu_run() to only save and restore callee saved registers. It is always called using the standard ABIs, so the caller will preserve any other registers that need preserving. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13208/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:19 UTC |
ca64c2b | Paul Burton | 06 May 2016, 13:36:20 UTC | MIPS: KVM: Abstract guest ASID mask In preparation for supporting varied widths of ASID mask in the kernel in general, switch KVM's guest ASIDs to a new KVM_ENTRYHI_ASID definition based on the 8-bit MIPS_ENTRYHI_ASID instead of ASID_MASK. It could potentially be used to support extended guest ASIDs in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13207/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:19 UTC |
9b5c339 | James Hogan | 06 May 2016, 13:36:19 UTC | MIPS: Add & use CP0_EntryHi ASID definitions Add definitions for the ASID field in CP0_EntryHi (along with the soon to be used ASIDX field), and use them in a few previously hardcoded cases. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13205/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:18 UTC |
5fb59fd | James Hogan | 06 May 2016, 13:36:18 UTC | MIPS: KVM/locore.S: Don't preserve host ASID around vcpu_run MIPS KVM uses different ASIDs for guest execution than for the host. The host ASID is saved on the stack when entering the guest with __kvm_mips_vcpu_run(), and restored again before returning back to the caller (exit to userland). - This does not take into account that pre-emption may have taken place during that time, which may have started a new ASID cycle and resulted in that process' ASID being invalidated and reused. - This does not take into account that the process may have migrated to a different CPU during that time, with a different ASID assignment since they are managed per-CPU. - It is actually redundant, since the host ASID will be restored correctly by kvm_arch_vcpu_put(), which is called almost immediately after kvm_arch_vcpu_ioctl_run() returns. Therefore drop this code from locore.S Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13206/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:18 UTC |
97b9210 | John Crispin | 05 May 2016, 07:57:56 UTC | MIPS: Change my email address The old address is no longer valid. Use the my new one instead. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13201/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:18 UTC |
bdb40e8 | John Crispin | 05 May 2016, 07:57:55 UTC | MAINTAINERS: Change my email address The old address is no longer valid. Use the my new one instead. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13200/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:17 UTC |
87321fd | Paul Burton | 06 May 2016, 12:35:03 UTC | MIPS: Implement __arch_bitrev* using bitswap for MIPSr6 Release 6 of the MIPS architecture introduced the bitswap instruction, which reverses the bits within each byte of a word. Make use of this instruction to implement the __arch_bitrev* functions, which should be faster for most MIPSr6 CPUs, reduces code size slightly and allows us to avoid the lookup table used by the generic implementation, saving 256 bytes in the kernel binary by dropping that. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13204/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:17 UTC |
015aa05 | Anna-Maria Gleixner | 02 May 2016, 09:00:49 UTC | MIPS: Remove no longer needed work_on_cpu() call Since commit 3b9d6da67e11 ("cpu/hotplug: Fix rollback during error-out in __cpu_disable()") it is ensured that callbacks of CPU_ONLINE and CPU_DOWN_PREPARE are processed on the hotplugged CPU. Due to this work_on_cpu() calls are no longer required. Replace work_on_cpu() with a direct call of mips_cdmm_bus_up() or mips_cdmm_bus_down(). Description of those functions are adapted. Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: rt@linutronix.de Patchwork: https://patchwork.linux-mips.org/patch/13197/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:17 UTC |
e8b5325 | Sergey Ryazanov | 30 August 2014, 02:06:28 UTC | MIPS: make PCI_DMA_BUS_IS_PHYS=1 constant No one of supported MIPS machines has an IOMMU unit, so we can safely define PCI_DMA_BUS_IS_PHYS = 1. Also remove iommu flag from the pci controller structure, since it is useless. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7604/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:17 UTC |
1e321fa | Leonid Yegoshin | 15 May 2015, 01:34:43 UTC | MIPS64: Support of at least 48 bits of SEGBITS SEGBITS is 40 bits or more, depending on CPU type. Introduces optional support for 48 bits of application virtual address space. Only 16K and 64K pages are supported. Enabling will result in a memory overhead of a small number of pages for small applications. For 64K pages a 3rd level of page tables is required which has some impact during software TLB refill. [ralf@linux-mips.org: Fixed things raised in the review of the version posted and changed kconfig to be a bit more userfriendly.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: aleksey.makarov@auriga.com Cc: james.hogan@imgtec.com Cc: paul.burton@imgtec.com Cc: david.daney@cavium.com Cc: peterz@infradead.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: davidlohr@hp.com Cc: kirill@shutemov.name Cc: akpm@linux-foundation.org Cc: mingo@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10051/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:16 UTC |
7939469 | Leonid Yegoshin | 19 October 2015, 18:39:55 UTC | MIPS64: signal: Fix o32 sigaction syscall MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly set to processing aka rt_sigaction() variant only. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: paul.burton@imgtec.com Cc: richard@nod.at Cc: luto@amacapital.net Cc: alex.smith@imgtec.com Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: mpe@ellerman.id.au Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11321/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:16 UTC |
cb80b2a | Leonid Yegoshin | 20 November 2015, 01:38:21 UTC | MIPS: remove aliasing alignment if HW has antialising support MIPS hardware may have an antialising support and it works even page size is small. Setup a shared memory aliasing mask to page size if hardware has an antialising support. Big shared memory mask forces a disruption in page address assignment and that corrupts Android library memory handling. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: cernekee@gmail.com Cc: paul.gortmaker@windriver.com Cc: kumba@gentoo.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11516/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:16 UTC |
201233e | Tony Wu | 04 December 2015, 11:41:12 UTC | MIPS: traps: remove unused variable flags is indeed unused. Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11699/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:15 UTC |
1e820da | Huacai Chen | 03 March 2016, 01:45:13 UTC | MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer), Fast TLB refill support, etc. This patch introduce a config option, CONFIG_LOONGSON3_ENHANCEMENT, to enable those enhancements which are not probed at run time. If you want a generic kernel to run on all Loongson 3 machines, please say 'N' here. If you want a high-performance kernel to run on new Loongson 3 machines only, please say 'Y' here. Some additional explanations: 1) SFB locates between core and L1 cache, it causes memory access out of order, so writel/outl (and other similar functions) need a I/O reorder barrier. 2) Loongson 3 has a bug that di instruction can not save the irqflag, so arch_local_irq_save() is modified. Since CPU_MIPSR2 is selected by CONFIG_LOONGSON3_ENHANCEMENT, generic kernel doesn't use ei/di at all. 3) CPU_HAS_PREFETCH is selected by CONFIG_LOONGSON3_ENHANCEMENT, so MIPS_CPU_PREFETCH (used by uasm) probing is also put in this patch. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:15 UTC |
380cd58 | Huacai Chen | 03 March 2016, 01:45:12 UTC | MIPS: Loongson-3: Fast TLB refill handler Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which can be used for fast TLB refill. [ralf@linux-mips.org: Resolve conflict.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12754/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:15 UTC |
06e4814 | Huacai Chen | 03 March 2016, 01:45:11 UTC | MIPS: Loongson: Invalidate special TLBs when needed Loongson-2 has a 4 entry itlb which is a subset of jtlb, Loongson-3 has a 4 entry itlb and a 4 entry dtlb which are subsets of jtlb. We should write diag register to invalidate itlb/dtlb when flushing jtlb because itlb/dtlb are not totally transparent to software. For Loongson-3A R2 (and newer), we should invalidate ITLB, DTLB, VTLB and FTLB before we enable/disable FTLB. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12753/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:14 UTC |
37fbe8f | Huacai Chen | 03 March 2016, 01:45:10 UTC | MIPS: Loongson-3: Set cache flush handlers to cache_noop Loongson-3 maintains cache coherency by hardware, this means: 1) It's icache is coherent with dcache. 2) It's dcaches don't alias (maybe depend on PAGE_SIZE). 3) It maintains cache coherency across cores (and for DMA). So we can skip most cache flush operations by setting relevant handlers to `cache_noop' in `r4k_cache_init'. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12752/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:14 UTC |
b2edcfc | Huacai Chen | 03 March 2016, 01:45:09 UTC | MIPS: Loongson: Add Loongson-3A R2 basic support Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R2 revision of Loongson-3A: - Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache). - I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is 64 bytes. - 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way set-associative). - Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/ Execute-Inhibit. [ralf@linux-mips.org: Resolved merge conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12751/ Patchwork: https://patchwork.linux-mips.org/patch/13136/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:14 UTC |
2465351 | Huacai Chen | 17 March 2016, 12:41:07 UTC | MIPS: Loongson-3: Adjust irq dispatch to speedup processing This patch adjust the logic in mach_irq_dispatch(), allow multiple IPs handled in the same dispatching. This can speedup interrupt processing. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12891/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:14 UTC |
d051472 | Huacai Chen | 07 October 2015, 06:08:00 UTC | MIPS: Loongson-3: Move chipset ACPI code from drivers to arch SB700/SB710/SB800 chipset ACPI code is mostly Loongson-3 specific routines rather than a "platform driver". Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11273/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:13 UTC |
44896af | Antonio Ospite | 27 January 2016, 13:56:06 UTC | MIPS: BCM1480: bcm1480_regs.h: strip redundant comments Strip some comments which probably meant to repeat the same value of the define; they also contained a confusing 0x0x prefix. Signed-off-by: Antonio Ospite <ao2@ao2.it> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12254/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:13 UTC |
50af501 | James Hogan | 01 March 2016, 22:19:39 UTC | MIPS: Add and use watch register field definitions The files watch.c and ptrace.c contain various magic masks for WatchLo/WatchHi register fields. Add some definitions to mipsregs.h for these registers and make use of them in both watch.c and ptrace.c, hopefully making them more readable. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12729/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:13 UTC |
e233c73 | James Hogan | 01 March 2016, 22:19:38 UTC | MIPS: Add and use CAUSEF_WP definition do_watch() clears bit 22 of cause without using a CAUSEF_* definition from mipsregs.h. Add a definition for this bit (CAUSEF_WP) and make use of it. Also use clear_c0_cause() instead of manual read/modify/write. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:13 UTC |
b0d8a08 | Purna Chandra Mandal | 26 February 2016, 17:20:22 UTC | watchdog: pic32-dmt: Add PIC32 deadman timer driver Adds support for the deadman timer peripheral found on PIC32 class devices. The primary function of the deadman timer (DMT) is to reset the processor in the event of a software malfunction. The DMT is a free-running instruction fetch timer, which is clocked whenever an instruction fetch occurs until a count match occurs. Instructions are not fetched when the processor is in sleep mode. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:12 UTC |
bfa4326 | Purna Chandra Mandal | 26 February 2016, 17:20:21 UTC | dt/bindings: Add bindings for PIC32 deadman timer peripheral Document the devicetree bindings for the deadman timer peripheral found on Microchip PIC32 SoC class devices. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: Guenter Roeck <linux@roeck-us.net> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12702/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:12 UTC |
8f91fc5 | Joshua Henderson | 26 February 2016, 17:19:28 UTC | watchdog: pic32-wdt: Add PIC32 watchdog driver Add support for the watchdog peripheral found on PIC32 class devices. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:12 UTC |
80c2902 | Joshua Henderson | 26 February 2016, 17:19:27 UTC | dt/bindings: Add bindings for PIC32 watchdog peripheral Document the devicetree bindings for the watchdog peripheral found on Microchip PIC32 SoC class devices. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: Guenter Roeck <linux@roeck-us.net> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:12 UTC |
ba837d3 | Andrzej Hajda | 15 February 2016, 14:35:20 UTC | MIPS: module: fix incorrect IS_ERR_VALUE macro usages IS_ERR_VALUE macro should be used only with unsigned long type. Specifically it works incorrectly with longer types. The patch follows conclusion from discussion on LKML [1][2]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2120927 [2]: http://permalink.gmane.org/gmane.linux.kernel/2150581 [ralf@linux-mips.org: While it may not immediately be obvious, the type of st_value in the end is an unsigned long equivalent so the invocation of IS_ERR_VALUE() was valid but I'm applying the patch anyway for clarity.] Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12553/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:11 UTC |
acd9e20 | Maciej W. Rozycki | 13 November 2015, 00:48:48 UTC | MIPS: math-emu: Always propagate sNaN payload in quieting Propagate sNaN payload in quieting in the legacy-NaN mode as well. If clearing the quiet bit would produce infinity, then set the next lower trailing significand field bit, matching the SB-1 and BMIPS5000 hardware implementations. Some other MIPS FPU hardware implementations do produce the default qNaN bit pattern instead. This reverts some changes made for semantics preservation with commit dc3ddf42 [MIPS: math-emu: Update sNaN quieting handlers], consequently bringing back most of the semantics from before commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.], except from the qNaN produced in the infinity case. Previously the default qNaN bit pattern was produced in that case. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:11 UTC |
2e5832a | Maciej W. Rozycki | 13 November 2015, 00:48:39 UTC | MIPS: ELF: Restructure personality macros Update the ELF personality macros used for individual ABIs to make actions in the same order across all of them and match formatting too. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:11 UTC |
987e5b8 | James Hogan | 08 February 2016, 18:43:51 UTC | MIPS: Fix uapi include in exported asm/siginfo.h Since commit 8cb48fe169dd ("MIPS: Provide correct siginfo_t.si_stime"), MIPS' uapi/asm/siginfo.h has included uapi/asm-generic/siginfo.h directly before defining MIPS' struct siginfo, in order to get the necessary definitions needed for the siginfo struct without the generic copy_siginfo() hitting compiler errors due to struct siginfo not yet being defined. Now that the generic copy_siginfo() is moved out to linux/signal.h we can safely include asm-generic/siginfo.h before defining the MIPS specific struct siginfo, which avoids the uapi/ include as well as breakage due to generic copy_siginfo() being defined before struct siginfo. Reported-by: Christopher Ferris <cferris@google.com> Fixes: 8cb48fe169dd ("MIPS: Provide correct siginfo_t.si_stime") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Petr Malat <oss@malat.biz> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.0- Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:11 UTC |
ca9eb49 | James Hogan | 08 February 2016, 18:43:50 UTC | SIGNAL: Move generic copy_siginfo() to signal.h The generic copy_siginfo() is currently defined in asm-generic/siginfo.h, after including uapi/asm-generic/siginfo.h which defines the generic struct siginfo. However this makes it awkward for an architecture to use it if it has to define its own struct siginfo (e.g. MIPS and potentially IA64), since it means that asm-generic/siginfo.h can only be included after defining the arch-specific siginfo, which may be problematic if the arch-specific definition needs definitions from uapi/asm-generic/siginfo.h. It is possible to work around this by first including uapi/asm-generic/siginfo.h to get the constants before defining the arch-specific siginfo, and include asm-generic/siginfo.h after. However uapi headers can't be included by other uapi headers, so that first include has to be in an ifdef __kernel__, with the non __kernel__ case including the non-UAPI header instead. Instead of that mess, move the generic copy_siginfo() definition into linux/signal.h, which allows an arch-specific uapi/asm/siginfo.h to include asm-generic/siginfo.h and define the arch-specific siginfo, and for the generic copy_siginfo() to see that arch-specific definition. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Petr Malat <oss@malat.biz> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Christopher Ferris <cferris@google.com> Cc: linux-arch@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-ia64@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: <stable@vger.kernel.org> # 4.0- Patchwork: https://patchwork.linux-mips.org/patch/12478/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:10 UTC |
0e8c1a3 | Yang Shi | 20 February 2016, 01:04:07 UTC | MIPS: Octeon: Mark some functions __init in smp.c octeon_smp_setup and octeon_prepare_cpus are just used during initialization period, so mark them as __init. And, octeon_prepare_cpus is just used in smp.c, so make it static as well. Signed-off-by: Yang Shi <yang.shi@windriver.com> Cc: david.daney@cavium.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12574/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:10 UTC |
2d52ee8 | Álvaro Fernández Rojas | 09 April 2016, 10:57:49 UTC | MIPS: BMIPS: Improve BCM6368 device tree - Remove unneeded leds0 alias. - Switch to bcm6345-l1-intc interrupt controller. - Use interrupt-controller instead of periph_intc and cpu_intc. - Add uart1 node. - Single ohci and ehci nodes. - Avoid using underscores in node names. - Rename uart aliases to serial. - Remove blank line in cpus node. [ralf@linux-mips.org: fix references in bcm96368mvwg.dts so the file keeps building.] Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Cc: f.fainelli@gmail.com Cc: jogo@openwrt.org Cc: cernekee@gmail.com Cc: robh@kernel.org Cc: simon@fire.lp0.eu Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:10 UTC |
e3b992d | Álvaro Fernández Rojas | 09 April 2016, 10:57:48 UTC | MIPS: BMIPS: Improve BCM6328 device tree - Remove unneeded leds0 alias. - Switch to bcm6345-l1-intc interrupt controller. - Use interrupt-controller instead of periph_intc and cpu_intc. - Add uart1, ehci and ohci nodes. - Refactor syscon and syscon-reboot. - Avoid using underscores in node names. - Rename uart aliases to serial. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Cc: f.fainelli@gmail.com Cc: jogo@openwrt.org Cc: cernekee@gmail.com Cc: robh@kernel.org Cc: simon@fire.lp0.eu Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13043/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:09 UTC |
3652acd | Álvaro Fernández Rojas | 09 April 2016, 10:57:19 UTC | MIPS: BMIPS: Add support for BCM63268 This SoC is very similar to BCM63168 and Broadcom usually refers to them as BCM63268. Add BCM63268 and missing BCM63168 to device tree documentation. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Cc: f.fainelli@gmail.com Cc: jogo@openwrt.org Cc: cernekee@gmail.com Cc: robh@kernel.org Cc: simon@fire.lp0.eu Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13042/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> | 13 May 2016, 12:02:09 UTC |