Revision 8227746b95146c2921f83d2ae5f37ecd146592d8 authored by Elliot Saba on 21 October 2014, 20:18:59 UTC, committed by Elliot Saba on 21 October 2014, 22:05:51 UTC
1 parent 7b1eb64
Raw File
instcombine-llvm-3.3.patch
diff -u -r -N llvm-3.3.src/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp llvm-3.3/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
--- llvm-3.3.src/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp	2013-01-02 06:36:10.000000000 -0500
+++ llvm-3.3/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp	2014-06-18 23:11:49.000000000 -0400
@@ -754,7 +754,7 @@
       ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1);
       // If it's known zero, our sign bit is also zero.
       if (LHSKnownZero.isNegative())
-        KnownZero |= LHSKnownZero;
+        KnownZero.setBit(KnownZero.getBitWidth() - 1);
     }
     break;
   case Instruction::URem: {
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