https://github.com/torvalds/linux
Revision 82836372311a5cbf9cc5f4f47f9b56cb9edfe90d authored by Colin on 26 May 2008, 16:04:43 UTC, committed by YOSHIFUJI Hideaki on 04 June 2008, 19:02:32 UTC
I discover a strange behavior in [ipv4 in ipv6] tunnel. When IPv6 tunnel payload is less than 40(0x28), packet can be sent to network, received in physical interface, but not seen in IP tunnel interface. No counter increase in tunnel interface. Signed-off-by: YOSHIFUJI Hideaki <yoshfuji@linux-ipv6.org>
1 parent 24ef0da
Tip revision: 82836372311a5cbf9cc5f4f47f9b56cb9edfe90d authored by Colin on 26 May 2008, 16:04:43 UTC
[IPV6] TUNNEL6: Fix incoming packet length check for inter-protocol tunnel.
[IPV6] TUNNEL6: Fix incoming packet length check for inter-protocol tunnel.
Tip revision: 8283637
ma1.h
/*
* include/asm-v850/ma1.h -- V850E/MA1 cpu chip
*
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_MA1_H__
#define __V850_MA1_H__
/* Inherit more generic details from MA series. */
#include <asm/ma.h>
#define CPU_MODEL "v850e/ma1"
#define CPU_MODEL_LONG "NEC V850E/MA1"
/* Hardware-specific interrupt numbers (in the kernel IRQ namespace). */
#define IRQ_INTOV(n) (n) /* 0-3 */
#define IRQ_INTOV_NUM 4
#define IRQ_INTP(n) (0x4 + (n)) /* Pnnn (pin) interrupts */
#define IRQ_INTP_NUM 24
#define IRQ_INTCMD(n) (0x1c + (n)) /* interval timer interrupts 0-3 */
#define IRQ_INTCMD_NUM 4
#define IRQ_INTDMA(n) (0x20 + (n)) /* DMA interrupts 0-3 */
#define IRQ_INTDMA_NUM 4
#define IRQ_INTCSI(n) (0x24 + (n)*4)/* CSI 0-2 transmit/receive completion */
#define IRQ_INTCSI_NUM 3
#define IRQ_INTSER(n) (0x25 + (n)*4) /* UART 0-2 reception error */
#define IRQ_INTSER_NUM 3
#define IRQ_INTSR(n) (0x26 + (n)*4) /* UART 0-2 reception completion */
#define IRQ_INTSR_NUM 3
#define IRQ_INTST(n) (0x27 + (n)*4) /* UART 0-2 transmission completion */
#define IRQ_INTST_NUM 3
#define NUM_CPU_IRQS 0x30
/* The MA1 has a UART with 3 channels. */
#define V850E_UART_NUM_CHANNELS 3
#endif /* __V850_MA1_H__ */
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