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Revision 8e2f3bce05e056575c2c84a344a8291fdabb5f21 authored by Doug Smythies on 08 August 2017, 21:12:49 UTC, committed by Rafael J. Wysocki on 10 August 2017, 23:27:41 UTC 
cpufreq: x86: Disable interrupts during MSRs reading
 
According to Intel 64 and IA-32 Architectures SDM, Volume 3,
Chapter 14.2, "Software needs to exercise care to avoid delays
between the two RDMSRs (for example interrupts)".

So, disable interrupts during reading MSRs IA32_APERF and IA32_MPERF.

See also: commit 4ab60c3f32c7 (cpufreq: intel_pstate: Disable
interrupts during MSRs reading).

Signed-off-by: Doug Smythies <dsmythies@telus.net>
Reviewed-by: Len Brown <len.brown@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
1 parent aae4e7a
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*.c   diff=cpp
*.h   diff=cpp
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