Revision 9095adaab8c1d82707e4e9961b6ad79b62f3361b authored by Quinn Tran on 10 February 2016, 23:59:13 UTC, committed by Nicholas Bellinger on 11 February 2016, 07:08:55 UTC
Signed-off-by: Quinn Tran <quinn.tran@qlogic.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Bart Van Assche <bart.vanassche@sandisk.com> Fixes: fb3269b ("qla2xxx: Add selective command queuing") Signed-off-by: Himanshu Madhani <himanshu.madhani@qlogic.com> Signed-off-by: Nicholas Bellinger <nab@linux-iscsi.org>
1 parent 2e498f2
cpu_families.txt
CPU Families
============
This document tries to summarise some of the different cpu families that exist
and are supported by arch/powerpc.
Book3S (aka sPAPR)
------------------
- Hash MMU
- Mix of 32 & 64 bit
+--------------+ +----------------+
| Old POWER | --------------> | RS64 (threads) |
+--------------+ +----------------+
|
|
v
+--------------+ +----------------+ +------+
| 601 | --------------> | 603 | ---> | e300 |
+--------------+ +----------------+ +------+
| |
| |
v v
+--------------+ +----------------+ +-------+
| 604 | | 750 (G3) | ---> | 750CX |
+--------------+ +----------------+ +-------+
| | |
| | |
v v v
+--------------+ +----------------+ +-------+
| 620 (64 bit) | | 7400 | | 750CL |
+--------------+ +----------------+ +-------+
| | |
| | |
v v v
+--------------+ +----------------+ +-------+
| POWER3/630 | | 7410 | | 750FX |
+--------------+ +----------------+ +-------+
| |
| |
v v
+--------------+ +----------------+
| POWER3+ | | 7450 |
+--------------+ +----------------+
| |
| |
v v
+--------------+ +----------------+
| POWER4 | | 7455 |
+--------------+ +----------------+
| |
| |
v v
+--------------+ +-------+ +----------------+
| POWER4+ | --> | 970 | | 7447 |
+--------------+ +-------+ +----------------+
| | |
| | |
v v v
+--------------+ +-------+ +----------------+
| POWER5 | | 970FX | | 7448 |
+--------------+ +-------+ +----------------+
| | |
| | |
v v v
+--------------+ +-------+ +----------------+
| POWER5+ | | 970MP | | e600 |
+--------------+ +-------+ +----------------+
|
|
v
+--------------+
| POWER5++ |
+--------------+
|
|
v
+--------------+ +-------+
| POWER6 | <-?-> | Cell |
+--------------+ +-------+
|
|
v
+--------------+
| POWER7 |
+--------------+
|
|
v
+--------------+
| POWER7+ |
+--------------+
|
|
v
+--------------+
| POWER8 |
+--------------+
+---------------+
| PA6T (64 bit) |
+---------------+
IBM BookE
---------
- Software loaded TLB.
- All 32 bit
+--------------+
| 401 |
+--------------+
|
|
v
+--------------+
| 403 |
+--------------+
|
|
v
+--------------+
| 405 |
+--------------+
|
|
v
+--------------+
| 440 |
+--------------+
|
|
v
+--------------+ +----------------+
| 450 | --> | BG/P |
+--------------+ +----------------+
|
|
v
+--------------+
| 460 |
+--------------+
|
|
v
+--------------+
| 476 |
+--------------+
Motorola/Freescale 8xx
----------------------
- Software loaded with hardware assist.
- All 32 bit
+-------------+
| MPC8xx Core |
+-------------+
Freescale BookE
---------------
- Software loaded TLB.
- e6500 adds HW loaded indirect TLB entries.
- Mix of 32 & 64 bit
+--------------+
| e200 |
+--------------+
+--------------------------------+
| e500 |
+--------------------------------+
|
|
v
+--------------------------------+
| e500v2 |
+--------------------------------+
|
|
v
+--------------------------------+
| e500mc (Book3e) |
+--------------------------------+
|
|
v
+--------------------------------+
| e5500 (64 bit) |
+--------------------------------+
|
|
v
+--------------------------------+
| e6500 (HW TLB) (Multithreaded) |
+--------------------------------+
IBM A2 core
-----------
- Book3E, software loaded TLB + HW loaded indirect TLB entries.
- 64 bit
+--------------+ +----------------+
| A2 core | --> | WSP |
+--------------+ +----------------+
|
|
v
+--------------+
| BG/Q |
+--------------+
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