Revision - 914988e - parisc: Restore __ldcw_align for PA-RISC 2.0 processors - origin: https://github.com/torvalds/linux

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08 September 2024, 02:26:05 UTC

Revision 914988e099fc658436fbd7b8f240160c352b6552 authored by John David Anglin on 19 September 2023, 17:51:40 UTC, committed by Helge Deller on 07 October 2023, 18:30:16 UTC

parisc: Restore __ldcw_align for PA-RISC 2.0 processors

Back in 2005, Kyle McMartin removed the 16-byte alignment for
ldcw semaphores on PA 2.0 machines (CONFIG_PA20). This broke
spinlocks on pre PA8800 processors. The main symptom was random
faults in mmap'd memory (e.g., gcc compilations, etc).

Unfortunately, the errata for this ldcw change is lost.

The issue is the 16-byte alignment required for ldcw semaphore
instructions can only be reduced to natural alignment when the
ldcw operation can be handled coherently in cache. Only PA8800
and PA8900 processors actually support doing the operation in
cache.

Aligning the spinlock dynamically adds two integer instructions
to each spinlock.

Tested on rp3440, c8000 and a500.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Link: https://lore.kernel.org/linux-parisc/6b332788-2227-127f-ba6d-55e99ecf4ed8@bell.net/T/#t
Link: https://lore.kernel.org/linux-parisc/20050609050702.GB4641@roadwarrior.mcmartin.ca/
Cc: stable@vger.kernel.org
Signed-off-by: Helge Deller <deller@gmx.de>

1 parent d3b3c63

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Tip revision: 914988e099fc658436fbd7b8f240160c352b6552 authored by John David Anglin on 19 September 2023, 17:51:40 UTC
parisc: Restore __ldcw_align for PA-RISC 2.0 processors

Tip revision: 914988e

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parisc: Restore __ldcw_align for PA-RISC 2.0 processors

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