https://github.com/torvalds/linux
Revision 9209fb51896fe0eef8dfac85afe1f357e9265c0d authored by Christoph Hellwig on 07 November 2019, 09:20:39 UTC, committed by Paul Walmsley on 20 December 2019, 11:40:24 UTC
The sifive_l2_cache.c is in no way related to RISC-V architecture
memory management.  It is a little stub driver working around the fact
that the EDAC maintainers prefer their drivers to be structured in a
certain way that doesn't fit the SiFive SOCs.

Move the file to drivers/soc and add a Kconfig option for it, as well
as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
[paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
1 parent 01f52e1
History
Tip revision: 9209fb51896fe0eef8dfac85afe1f357e9265c0d authored by Christoph Hellwig on 07 November 2019, 09:20:39 UTC
riscv: move sifive_l2_cache.c to drivers/soc
Tip revision: 9209fb5
File Mode Size
Documentation
LICENSES
arch
block
certs
crypto
drivers
fs
include
init
ipc
kernel
lib
mm
net
samples
scripts
security
sound
tools
usr
virt
.clang-format -rw-r--r-- 15.0 KB
.cocciconfig -rw-r--r-- 59 bytes
.get_maintainer.ignore -rw-r--r-- 71 bytes
.gitattributes -rw-r--r-- 62 bytes
.gitignore -rw-r--r-- 1.7 KB
.mailmap -rw-r--r-- 14.0 KB
COPYING -rw-r--r-- 423 bytes
CREDITS -rw-r--r-- 97.3 KB
Kbuild -rw-r--r-- 1.3 KB
Kconfig -rw-r--r-- 595 bytes
MAINTAINERS -rw-r--r-- 526.3 KB
Makefile -rw-r--r-- 59.4 KB
README -rw-r--r-- 727 bytes

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