Revision 92e55a865bc7b3f89bb8c684f6846651868ee7d7 authored by Palmer Dabbelt on 25 August 2022, 23:06:49 UTC, committed by Palmer Dabbelt on 25 August 2022, 23:32:39 UTC
Microchip RISC-V devicetree fixes for 6.0-rc3 Two sets of fixes this time around: - A fix for the interrupt ordering of the l2-cache controller. If the driver is enabled, it would spam the console /constantly/, rendering the system useless. - General cleanup for some bogus properties in the dt, part of my quest for zero dtbs_check warnings. On that note, the interrupt ordering adds a dtbs_check warning - but I considered that fixing the potentially useless system was more of a priority. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'dt-fixes-for-palmer-6.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git: riscv: dts: microchip: mpfs: remove pci axi address translation property riscv: dts: microchip: mpfs: remove bogus card-detect-delay riscv: dts: microchip: mpfs: remove ti,fifo-depth property riscv: dts: microchip: mpfs: fix incorrect pcie child node name riscv: dts: microchip: correct L2 cache interrupts
File | Mode | Size |
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.gitignore | -rw-r--r-- | 92 bytes |
Build | -rw-r--r-- | 170 bytes |
Makefile | -rw-r--r-- | 2.1 KB |
iio_event_monitor.c | -rw-r--r-- | 10.3 KB |
iio_generic_buffer.c | -rw-r--r-- | 18.0 KB |
iio_utils.c | -rw-r--r-- | 21.4 KB |
iio_utils.h | -rw-r--r-- | 2.6 KB |
lsiio.c | -rw-r--r-- | 3.7 KB |
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