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02 December 2022, 17:28:11 UTC
Revision 93dc68876b608da041fe40ed39424b0fcd5aa2fb authored by Catalin Marinas on 26 March 2013, 22:35:04 UTC, committed by Russell King on 03 April 2013, 15:45:49 UTC 
ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)
 
On Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down
all use of the old entries. This patch implements the erratum workaround
which consists of:

1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation.
2. Send IPI to the CPUs that are running the same mm (and ASID) as the
   one being invalidated (or all the online CPUs for global pages).
3. CPU receiving the IPI executes a DMB and CLREX (part of the exception
   return code already).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1 parent 6e7acee
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Tip revision: 93dc68876b608da041fe40ed39424b0fcd5aa2fb authored by Catalin Marinas on 26 March 2013, 22:35:04 UTC
ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)
Tip revision: 93dc688
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