Revision 9bd9ddb7f89edae241d2da78e3119f226b9b0cf6 authored by Jisheng Zhang on 30 March 2016, 11:55:21 UTC, committed by David S. Miller on 31 March 2016, 19:15:01 UTC
The mvneta is also used in some Marvell berlin family SoCs which may
have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
usage with L1_CACHE_BYTES.

And since dma_alloc_coherent() is always cacheline size aligned, so
remove the align checks.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent b7854ef
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.get_maintainer.ignore -rw-r--r-- 31 bytes
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