| 9d15ac7 | Guillaume Revaillot | 16 October 2019, 14:48:09 UTC | cortex: FAULTMASK does not exist on armv6m. | 04 January 2020, 21:53:34 UTC |
| db6237c | Guillaume Revaillot | 30 December 2019, 17:50:18 UTC | stm32: extract g0 exti stuff to exti_common_v2. stm32l5 basically uses the same stuff. | 01 January 2020, 18:47:13 UTC |
| f7a952c | Sam Protsenko | 15 December 2019, 21:03:53 UTC | stm32: Fix typo in RCC related comments ABP -> APB Signed-off-by: Sam Protsenko <joe.skb7@gmail.com> | 26 December 2019, 13:46:30 UTC |
| df15b26 | Karl Palsson | 25 December 2019, 21:04:17 UTC | usb: hid: add a stub file for doxygen Unlike with the doxygen source generation, we can't autoguess which of the class files are eligible automatically. Instead, make a stub hid file, (which we can now start adding to, if desired) and include it in all builds that include other class stubs. | 25 December 2019, 21:04:17 UTC |
| f2f5083 | Fabio Pugliese Ornellas | 09 November 2019, 20:32:13 UTC | usb: Add more HID Class constants | 25 December 2019, 20:44:46 UTC |
| aabd4da | Karl Palsson | 25 December 2019, 20:43:02 UTC | stm32g0: syscfg: doc: fix missing grouping | 25 December 2019, 20:43:02 UTC |
| 87dbf40 | Guillaume Revaillot | 28 August 2019, 16:04:02 UTC | stm32g0: rcc: group rcc_registers and registers values | 25 December 2019, 20:34:11 UTC |
| f70f0d0 | Guillaume Revaillot | 03 July 2019, 14:00:13 UTC | stm32g0: pwr: doc: remove duplicated ingroup | 25 December 2019, 20:34:11 UTC |
| 48afe3c | Guillaume Revaillot | 17 September 2019, 17:00:31 UTC | stm32g0: flash: fix wrong comment. | 25 December 2019, 20:34:11 UTC |
| ebd265c | Guillaume Revaillot | 06 September 2019, 16:01:35 UTC | stm32g0: rng: typo in header. | 25 December 2019, 20:34:11 UTC |
| 169d235 | Guillaume Revaillot | 08 November 2019, 15:23:18 UTC | stm32: lptimer: fix documentation | 25 December 2019, 20:34:11 UTC |
| 070058f | Guillaume Revaillot | 08 November 2019, 14:24:53 UTC | stm32: adc: doc fix declare chselr group in v2 single header, where adc_chselr reg is declared | 25 December 2019, 20:34:11 UTC |
| e7c8f18 | Guillaume Revaillot | 08 November 2019, 13:47:11 UTC | stm32: adc: group adc_registers | 25 December 2019, 20:34:11 UTC |
| 86b4cf6 | Karl Palsson | 25 December 2019, 20:30:17 UTC | stm32h7: fix typo in doxygen description | 25 December 2019, 20:30:17 UTC |
| a5b6673 | Karl Palsson | 25 December 2019, 20:30:03 UTC | stm32: usart-v2: fix some doxygen linking problems | 25 December 2019, 20:30:03 UTC |
| aabefea | Brian Viele | 12 December 2019, 01:07:49 UTC | stm32h7: usart: support new fifo features Supported by H7 and G4 varieties at present. | 25 December 2019, 20:29:24 UTC |
| fa3c1df | Karl Palsson | 25 December 2019, 13:43:03 UTC | pac55xx: fix up and simplify some doxygen | 25 December 2019, 13:44:49 UTC |
| a3406f1 | Brian Viele | 02 December 2019, 02:46:07 UTC | pac55xx: gpio: Initial Implementation of PAC55xx GPIO Driver * Conforms mostly to the STM32 GPIO API where possible. * Supports pin configuration (direction, pull-up/down, etc.) as well as pinmux configuration. * Supports set/clear/get operations to the GPIO port/pins. * Created base doxy header and groups to align with existing formatting. | 25 December 2019, 13:44:35 UTC |
| 9598b7f | Karl Palsson | 12 December 2019, 20:37:58 UTC | doc: stm32:rcc: flag "better" periph enable options The original rcc_peripheral_enable_clock aren't explicitly deprecated, as they do let you enable multiple periphs in one call. But they're error prone, from user feedback, so update the docs to ensure people know what the other options are. | 12 December 2019, 20:37:58 UTC |
| 85275fd | Karl Palsson | 12 December 2019, 20:36:51 UTC | stm32f1: adc: doc: drop undocumented examples There's already example code, this was just conflicting extra code that wasn't being included in doxygen anyway. | 12 December 2019, 20:36:51 UTC |
| 557e7aa | Karl Palsson | 12 December 2019, 20:35:57 UTC | doc: avoid usage of rcc_peripheral_enable_clock Use the simpler, safer rcc_periph_clock_enable instead | 12 December 2019, 20:35:57 UTC |
| 4a9ba30 | TomasPech | 11 December 2019, 23:32:00 UTC | stm32f4: rcc_clock_setup_pll() correctly enable PWR Original code used the special macros for rcc_periph_clock_enable instead of the appropraite APB1ENR bit definition. Switch to the correct, simpler form, using the correct parameter. | 12 December 2019, 20:12:27 UTC |
| 3c34f00 | Darrell Harmon | 10 December 2019, 20:33:49 UTC | genlink: avoid creating blank linker script if gcc fails When piping to a file, if arm-none-eabi-gcc is not present in the path, a blank linker script is created with genlink. After sourcing a bash script to add GCC to the path, the linker script doesn't get rebuilt due to a fresh timestamp despite failing to generate. | 11 December 2019, 09:42:05 UTC |
| 9af9a1d | Mathias Nord | 03 December 2019, 13:45:47 UTC | stm32g0: use spi v2 | 03 December 2019, 13:45:47 UTC |
| 867e382 | Karl Palsson | 28 November 2019, 22:25:36 UTC | readme: add h7 and g0 | 28 November 2019, 22:25:36 UTC |
| af384db | Karl Palsson | 28 November 2019, 22:16:54 UTC | doc: fix some broken groups uncovered while reviewing h7 code | 28 November 2019, 22:16:54 UTC |
| af8a177 | Karl Palsson | 28 November 2019, 22:16:34 UTC | stm32h7: doc: fix some missing group definitions | 28 November 2019, 22:16:34 UTC |
| 5330243 | Brian Viele | 07 November 2019, 02:32:54 UTC | stm32h7: Initial introduction into libopencm3. Updates to a base set of includes to map to the h7 include files which are mainly based on the f7 versions for simple devices (e.g. SPI, USART, GPIO). Custom files that have been implemented from the datasheet/ref manual include the memory map, RCC, PWR definitions, and irq.json file for generation of nvic files for interrupt mapping. Additional functionality, especially PLL and tweaks for non-F7 compatible implementations coming in future commits. Added documentation tree configuration. Reviewed-by: Karl Palsson <karlp@tweak.net.au> Changed dmaX_streamX to dmaX_strX in a few places for consistency | 28 November 2019, 22:15:24 UTC |
| da0c6a6 | Karl Palsson | 28 November 2019, 11:43:01 UTC | swm050: wdt: doxygen polish | 28 November 2019, 11:43:01 UTC |
| 47b59e2 | Caleb Szalacinski | 27 October 2019, 20:12:09 UTC | swm050: Adds WDT peripheral Reviewed-by: Karl Palsson <karlp@tweak.net.au> (Fixed an &| in wdt_set_time) | 28 November 2019, 11:42:31 UTC |
| dd18b9f | Brian Viele | 26 November 2019, 19:18:37 UTC | Qorvo pac55xx: initial support Qorvo (Nee Active Semi) PAC55xx "Intelligent Motor Control" parts, cortex-m4 SoCs | 26 November 2019, 23:28:02 UTC |
| bcfdcc0 | Guillaume Revaillot | 31 January 2019, 14:43:24 UTC | stm32g0: add syscfg header. | 25 November 2019, 20:49:20 UTC |
| 0a68b01 | larchuto | 21 November 2019, 17:59:32 UTC | stm32l4: Fix typo impacting uart4 and uart5 | 21 November 2019, 17:59:32 UTC |
| 38b45c8 | Guillaume Revaillot | 21 January 2019, 14:36:49 UTC | stm32g0: add adc. v2 "single" peripheral with a couple of tweaks : - added registers to configure two additionnal advanced analog watchdog. - different adc sampling time time based on channel groups. - 8 steps adc sequence injection, using chselr/chselrmode. And a note on the rm explaining that after every configuration change to ADC_CFGR1's SCANDIR or CHSELRMOD or CHSELR register, user need to check that configuration is applied before any other modification / adc conversion start.. making adc_set_reqular a bit painfull to read.. | 08 November 2019, 14:19:17 UTC |
| a34da53 | Guillaume Revaillot | 12 June 2019, 09:52:04 UTC | stm32g0: add dmamux DMAMUX peripheral is a dma request router/trigger, present on g0, wb, h7 and l4+. Basically it allows to easily map peripheral requests to whatever dma channel we want to use (similarily to the DMA_CSELR register, but without limitation) but, it also also adds some clever dma request synchronization and even some dma request generation logic via internal request generator "channels", allowing some requests chaining, or triggering reqs from non dma capable peripherals. nb: g0 only features 1 dmamux bloc, supports 7 irq and 4 generators, l4+ supports 13 dma channels and 3 generators and h7 has two dmamuxes, with support for the 15 dma channels and 7 generators - so as much CxCR and RGxCR register - but they are bit to bit compatible - excluding of course the sync/sig and dma requests id mappings. btw, currently, request generator channels are defined in common header, but maybe we should define them in device header ? or we dont care (like for dma channels, only defined in dma_f24 but not for other devices ?). See ST AN5224 for more information | 08 November 2019, 12:47:41 UTC |
| b9f183b | Guillaume Revaillot | 31 January 2019, 17:31:23 UTC | stm32g0: add dma. same same, bit for bit, except not ;) - Channel request mapping now depends on a new DMAMUX peripheral, and there's no default preset. So, before enabling dma channel after its configuration, request must be configured by : dmamux_set_dma_channel_request(DMAMUX1, DMA_CHANNELx, request_number_from_datasheet); | 08 November 2019, 12:47:41 UTC |
| 7a27397 | Karl Palsson | 06 November 2019, 19:44:41 UTC | stm32: rtcv2: don't shift the "month tens" bit None of the other masks are shifted, don't shift this field either. Fixes: https://github.com/libopencm3/libopencm3/issues/1123 | 06 November 2019, 19:45:20 UTC |
| 6d91399 | Karl Palsson | 22 October 2019, 10:35:04 UTC | devices.data: add some more l0 parts | 22 October 2019, 10:35:04 UTC |
| 88b32e3 | Karl Palsson | 22 October 2019, 10:23:18 UTC | devices.data: stm32f4: add all missing parts | 22 October 2019, 10:23:18 UTC |
| af05098 | Eivind Alexander Bergem | 22 October 2019, 07:04:53 UTC | devices.data: Added stm32f410 | 22 October 2019, 07:04:53 UTC |
| 2b54119 | Karl Palsson | 18 October 2019, 22:38:16 UTC | cm3: scs: drop all duplicate information Keeps the best version of the documentation. Fixes: https://github.com/libopencm3/libopencm3/pull/269 | 18 October 2019, 22:38:16 UTC |
| 833da4b | Karl Palsson | 18 October 2019, 22:33:23 UTC | cm3: extract SCB SHPR to the SCB world it belongs to Pull out the duplicate into the right file, keeping the newly fixed version. | 18 October 2019, 22:33:23 UTC |
| 3ebd71b | Karl Palsson | 18 October 2019, 22:29:13 UTC | cm3: extract Coresight LSR/LAR definitions Use a single point of definition for the offset, and add it where it was missing. | 18 October 2019, 22:29:13 UTC |
| d8579dd | Matt Anderson | 19 June 2019, 08:01:37 UTC | CortexM0: IPR and SHPR are only word addressable For ARMv6M, the IPR and SHPR registers are accessible only when adddressed with a 32bit word read or write. Currently in libopencm3 all NVIC interrupt priority register accesses are made using an 8bit read or write, which results in the hardware ignoring the write or always returning 0 on read. Address this by introducing NVIC_IPR32() and SCS_SHPR32() macro and conditional implementation of nvic_set_priority when building for cortex-m0. See ARMv6M developer documentation: IPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/Cihgjeed.html SHPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CIAGECDD.html | 17 October 2019, 21:26:13 UTC |
| baa2f13 | Karl Palsson | 17 October 2019, 11:41:02 UTC | swm050: doc: tweak peripheral apis groupings Makes it more consistent with the other families. | 17 October 2019, 11:41:55 UTC |
| 3c4ee6f | Caleb Szalacinski | 21 September 2019, 20:43:50 UTC | SWM050: Finishes GPIO, IAP flash, sysclock, sleep/stop, and the sysctl memory map. Updates the main memory map and the makefile. Adds the SWM050 to devices.data, so that a linker script can be automatically generated. Reviewed-by: Karl Palsson <karlp@tweak.net.au> | 17 October 2019, 11:41:33 UTC |
| 1fbfdec | Bryan PEREIRA | 16 October 2019, 09:06:41 UTC | stm32f3: Add SPI4 BASE | 16 October 2019, 14:41:00 UTC |
| 77d96a3 | Nicholas Rossomando | 12 October 2019, 06:02:23 UTC | stm32l0: crc: enable common code | 12 October 2019, 14:11:39 UTC |
| b5d66ee | Karl Palsson | 03 October 2019, 11:37:47 UTC | devices.data: add all missing stm32f3 parts Filled missing variants, added missing families, corrected one or two mistakes in ccm availability Fixes: https://github.com/libopencm3/libopencm3/pull/1109 | 03 October 2019, 11:37:47 UTC |
| 66e6a20 | Karl Palsson | 30 September 2019, 10:28:21 UTC | doc: stm32f1: gpio: remove redundant doxygen types Fixes https://github.com/libopencm3/libopencm3/issues/1108 | 30 September 2019, 10:28:21 UTC |
| ec2d964 | Jonathan Halmen | 27 July 2019, 17:29:47 UTC | stm32f4: rcc: add plli2s config function | 27 September 2019, 13:55:56 UTC |
| 203d0ca | Jonathan Halmen | 27 July 2019, 17:09:43 UTC | stm32f4: rcc: remove unnecessary pllsai functions existing standard functions for these are * rcc_osc_on(RCC_PLLSAI); * rcc_is_osc_ready(RCC_PLLSAI); | 27 September 2019, 13:43:06 UTC |
| 5fbe5c8 | Matthew Lai | 22 September 2019, 00:39:49 UTC | devices.data: Added STM32F7 value line devices with 64K flash | 23 September 2019, 22:45:36 UTC |
| b0c3de8 | Karl Palsson | 03 September 2019, 22:23:26 UTC | devices.data: add missing stm32f301 parts Fixes: https://github.com/libopencm3/libopencm3/issues/1098 | 03 September 2019, 22:23:26 UTC |
| 8a1cfa8 | Guillaume Revaillot | 28 August 2019, 16:04:02 UTC | stm32g0: use proper register for gpio peripheral clock sleep enable. Reviewed-by: Karl Palsson <karlp@tweak.net.au> | 28 August 2019, 20:54:35 UTC |
| 998e647 | Guillaume Revaillot | 28 August 2019, 10:03:55 UTC | stm32g0: memorymap: get rid of apb1/apb2 reference, device only has one apb. I apparently based memorymap.h on previously written header without noticing that g0 has only one apb despite a big hole in the memory space and addresses matching usual apb1/apb2 split.. | 28 August 2019, 10:03:55 UTC |
| 1928e6e | Guillaume Revaillot | 27 August 2019, 14:44:45 UTC | doc: typo | 28 August 2019, 01:41:14 UTC |
| 562dca7 | Guillaume Revaillot | 27 August 2019, 13:18:44 UTC | stm32f4: doc: f4 are cortex m4f based | 28 August 2019, 01:41:14 UTC |
| ec59779 | Guillaume Revaillot | 27 August 2019, 14:23:54 UTC | stm32g0: fix bad typos in memorymap, impacting tim1 and tim15-17. | 27 August 2019, 14:24:42 UTC |
| 7ff54cb | Karl Palsson | 22 August 2019, 09:52:14 UTC | devices.data: add more stm32l1 parts Fixes some eeprom sizes, and adds all the -a and -x suffix parts. Note that the explicit endings must be listed _before_ the base parts, otherwise the matcher will find the wild card first. Signed-off-by: Karl Palsson <karlp@etactica.com> | 22 August 2019, 10:01:11 UTC |
| 3eff201 | Guillaume Revaillot | 02 July 2019, 12:17:14 UTC | doc: stm32: adc: upgrade common_v2 documentation add register grouping, fixup comment have them pickedup by doxygen, align style and masks. | 06 July 2019, 15:38:49 UTC |
| 2035d84 | Guillaume Revaillot | 18 June 2019, 11:33:11 UTC | stm32: lptim: add base support Add basically what's needed to have some minimal but usefull subset of function for a timer: irqs, compare, period, out polarity, enable/disable and start. | 05 July 2019, 09:43:11 UTC |
| f99e711 | Guillaume Revaillot | 03 July 2019, 15:19:48 UTC | stm32g0: lptim: add additional cr bits and cfgr2 reg. | 05 July 2019, 09:43:11 UTC |
| 811aebf | Guillaume Revaillot | 18 June 2019, 12:06:09 UTC | stm32: lptimer: enable lptimer.h usage on f4,f7,l4 and g0 chips. | 05 July 2019, 08:48:55 UTC |
| 2975c31 | Guillaume Revaillot | 17 June 2019, 16:04:00 UTC | stm32: extract l0 lptimer stuff from timer.h to common lptimer.h lptimer peripheral is present on f4,f7,l0,l4,g0,g4 and prob others. Extract content from stm32l0 timer.h and make it usable by other chips. | 05 July 2019, 08:48:26 UTC |
| 689e326 | Guillaume Revaillot | 19 June 2019, 08:44:46 UTC | stm32f4: lptim1 sits at 0x40002400 on stm32f410, update memorymap | 02 July 2019, 16:27:43 UTC |
| 6894965 | Karl Palsson | 02 July 2019, 09:34:28 UTC | gadget0: f429: update to newest rcc api | 02 July 2019, 09:34:28 UTC |
| 43b6f33 | Karl Palsson | 28 June 2019, 21:44:44 UTC | gadget0: f4: update to newest rcc api | 28 June 2019, 21:45:14 UTC |
| 1519b43 | Karl Palsson | 28 June 2019, 21:37:31 UTC | gadget0: f4: PA9 is not an AF. It has never been an AF, it's always been an error to set this pin to AF. | 28 June 2019, 21:45:14 UTC |
| 7c24f0f | Karl Palsson | 28 June 2019, 21:11:06 UTC | gadget0: allow parallel submake allows "make -j10" work properly | 28 June 2019, 21:45:14 UTC |
| 8b4d952 | Karl Palsson | 26 June 2019, 12:42:34 UTC | doc: stm32f3: adc: add missing parameters Minor, link the adc peripheral parameter in a couple of places | 27 June 2019, 14:53:09 UTC |
| 9b3c813 | Karl Palsson | 26 June 2019, 12:33:57 UTC | doc: lm3s: escape email address to avoid xml interp | 27 June 2019, 14:53:09 UTC |
| 38d88c6 | Karl Palsson | 26 June 2019, 12:31:25 UTC | doc: stm32f0: rcc: add missing groups for pll factors and sources | 27 June 2019, 14:53:09 UTC |
| 06ee200 | Karl Palsson | 26 June 2019, 12:24:07 UTC | doc: gd32f1x0: merge flash and rcc into periperhal apis Instead of having some in peripheral_apis and some under the target itself | 27 June 2019, 14:53:09 UTC |
| 8744df1 | Karl Palsson | 25 June 2019, 14:20:12 UTC | doc: gd32: make groups match what's used. Fixes the missing top level groupings here. | 25 June 2019, 21:15:35 UTC |
| 0cd06bc | Karl Palsson | 25 June 2019, 14:00:53 UTC | doc: gd32/f1x0: fix missing tags, drop wrong tags Drop incorrect/redundant type information from doxygen parameters Adds groupings that are referred to. | 25 June 2019, 21:15:35 UTC |
| 1964fd7 | Karl Palsson | 25 June 2019, 13:41:08 UTC | doc: stm32f3: adc: register base addresses had landed outside a group | 25 June 2019, 21:15:35 UTC |
| 668cfb2 | Karl Palsson | 25 June 2019, 13:31:50 UTC | doc: cm3: scb: add basic documentation Adds a summary page, and now we have the existing functions documented. | 25 June 2019, 21:15:31 UTC |
| e5b5ba0 | Karl Palsson | 25 June 2019, 13:21:38 UTC | doc: cm3: dwt: include existing documentation | 25 June 2019, 21:15:24 UTC |
| 1b10a08 | Karl Palsson | 25 June 2019, 13:04:20 UTC | doc: cm3: mpu: fix typo | 25 June 2019, 21:15:19 UTC |
| 60991ac | Karl Palsson | 25 June 2019, 13:04:00 UTC | doc: cm3: nvic: convert existing docs to doxygen Make it visible | 25 June 2019, 21:15:19 UTC |
| 69ce9f8 | Karl Palsson | 25 June 2019, 13:02:18 UTC | doc: core cm3: standard titles easier on the eyes reading the list of docs | 25 June 2019, 21:15:19 UTC |
| f63145d | Karl Palsson | 25 June 2019, 12:52:58 UTC | doc: stm32f7: rcc: add missing top level groups | 25 June 2019, 21:15:19 UTC |
| 1f359e0 | Karl Palsson | 25 June 2019, 12:19:03 UTC | doc: efm32: tag USB files for doxygen generation | 25 June 2019, 21:15:19 UTC |
| 2d1277e | Karl Palsson | 25 June 2019, 12:06:47 UTC | doc: efm32: uart/usart provide common doxygen Fix some direct includes, tag properly, include a stub file to pull in shared header documentation and re-arrange some existing documentation to make it present nicely. | 25 June 2019, 21:15:19 UTC |
| 56265ad | Karl Palsson | 25 June 2019, 11:42:47 UTC | doc: efm32: rtc: tag and include in generated output Includes the sutb file ncessary to find shared headers without any apis | 25 June 2019, 21:15:19 UTC |
| 6df301a | Karl Palsson | 25 June 2019, 11:40:55 UTC | doc: efm32: timer: properly tag the shared header as well | 25 June 2019, 21:15:19 UTC |
| 9b3ab93 | Karl Palsson | 25 June 2019, 11:35:54 UTC | doc: efm32: wdog: include stub file Tags were added, but without the stub file, common headers aren't picked up by the auto source list generation | 25 June 2019, 21:15:19 UTC |
| 531aa7e | Karl Palsson | 25 June 2019, 11:24:44 UTC | doc: efm32: rmu: include in doxygen generation Include a stub .c file for shared code generation | 25 June 2019, 21:15:19 UTC |
| 75f6cbf | Karl Palsson | 25 June 2019, 11:18:44 UTC | doc: efm32: msc: tag for doxygen inclusion Includes a stub .c file to trigger common code generation | 25 June 2019, 21:15:19 UTC |
| c92f3dc | Karl Palsson | 25 June 2019, 11:11:27 UTC | doc: efm32: letimer: include tags for doxygen Include a stub .c file to document the shared headers. | 25 June 2019, 21:15:19 UTC |
| 25dc3a9 | Karl Palsson | 25 June 2019, 11:03:22 UTC | doc: efm32: i2c: tag for doxygen Includes a stub .c file until there are some APIs | 25 June 2019, 21:15:19 UTC |
| 4c01e47 | Karl Palsson | 25 June 2019, 10:58:19 UTC | doc: efm32: emu: tag for doxygen properly Requires a stub .c file to make the common files be included until we build some APIs. | 25 June 2019, 21:15:19 UTC |
| 764fbed | Karl Palsson | 25 June 2019, 09:38:42 UTC | doc: efm32: dac: fix up mising tags on common file | 25 June 2019, 21:15:19 UTC |
| 790d624 | Karl Palsson | 25 June 2019, 09:35:45 UTC | doc: efm32: burtc: tag properly for doxyen includes a stub .c file until there are APIs defined. | 25 June 2019, 21:15:19 UTC |
| aa99aba | Karl Palsson | 25 June 2019, 09:31:47 UTC | doc: efm32: prs: properly tag for doxygen | 25 June 2019, 21:15:19 UTC |
| 46514e7 | Karl Palsson | 25 June 2019, 09:27:42 UTC | doc: efm32: dma: tag headers properly | 25 June 2019, 21:15:19 UTC |
| 8d80db0 | Karl Palsson | 25 June 2019, 12:36:29 UTC | gendoxylist: sort headers This makes the doxygen lists much more rationally ordered. | 25 June 2019, 21:15:19 UTC |
| dc3bb24 | Karl Palsson | 22 June 2019, 01:50:23 UTC | doc: efm32: acmp: add missing file Classssssssic error. Don't git add the local file created. doh. | 22 June 2019, 01:50:23 UTC |
| 7e2cd05 | Karl Palsson | 22 June 2019, 01:36:06 UTC | doc: efm32: acmp: document, and include via peripheral_apis Requires a stub .c file as it has common includes with out any common code (yet) | 22 June 2019, 01:38:20 UTC |
