https://github.com/torvalds/linux
Revision 9fcf024dd6fae082f05e8c1fcdae23972b2f6971 authored by Vladimir Oltean on 27 December 2019, 00:59:54 UTC, committed by David S. Miller on 31 December 2019, 04:10:20 UTC
The PTP egress timestamp N must be captured from register PTPEGR_TS[n],
where n = 2 * PORT + TSREG. There are 10 PTPEGR_TS registers, 2 per
port. We are only using TSREG=0.
As opposed to the management slots, which are 4 in number
(SJA1105_NUM_PORTS, minus the CPU port). Any management frame (which
includes PTP frames) can be sent to any non-CPU port through any
management slot. When the CPU port is not the last port (#4), there will
be a mismatch between the slot and the port number.
Luckily, the only mainline occurrence with this switch
(arch/arm/boot/dts/ls1021a-tsn.dts) does have the CPU port as #4, so the
issue did not manifest itself thus far.
Fixes: 47ed985e97f5 ("net: dsa: sja1105: Add logic for TX timestamping")
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent 0caeaf6
Tip revision: 9fcf024dd6fae082f05e8c1fcdae23972b2f6971 authored by Vladimir Oltean on 27 December 2019, 00:59:54 UTC
net: dsa: sja1105: Take PTP egress timestamp by port, not mgmt slot
net: dsa: sja1105: Take PTP egress timestamp by port, not mgmt slot
Tip revision: 9fcf024
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