https://github.com/torvalds/linux
Revision 9fe17b5d47d3d3c85b35623dea8f571a184134c0 authored by Takashi Iwai on 12 May 2010, 08:32:42 UTC, committed by Takashi Iwai on 12 May 2010, 08:32:42 UTC
MIPS non-coherent archs need the noncached pgprot in mmap of PCM buffers. But, since the coherency needs to be checked dynamically via plat_device_is_coherent(), we need an ugly check dependent on MIPS in ALSA core code. This should be cleaned up in MIPS arch side (e.g. creating dma_mmap_coherent()) in near future. Tested-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
1 parent 6a45f78
Tip revision: 9fe17b5d47d3d3c85b35623dea8f571a184134c0 authored by Takashi Iwai on 12 May 2010, 08:32:42 UTC
ALSA: pcm - Use pgprot_noncached() for MIPS non-coherent archs
ALSA: pcm - Use pgprot_noncached() for MIPS non-coherent archs
Tip revision: 9fe17b5
Kconfig-nommu
#
# Kconfig for uClinux(non-paged MM) depend configurations
# Hyok S. Choi <hyok.choi@samsung.com>
#
config SET_MEM_PARAM
bool "Set flash/sdram size and base addr"
help
Say Y to manually set the base addresses and sizes.
otherwise, the default values are assigned.
config DRAM_BASE
hex '(S)DRAM Base Address' if SET_MEM_PARAM
default 0x00800000
config DRAM_SIZE
hex '(S)DRAM SIZE' if SET_MEM_PARAM
default 0x00800000
config FLASH_MEM_BASE
hex 'FLASH Base Address' if SET_MEM_PARAM
default 0x00400000
config FLASH_SIZE
hex 'FLASH Size' if SET_MEM_PARAM
default 0x00400000
config PROCESSOR_ID
hex 'Hard wire the processor ID'
default 0x00007700
depends on !CPU_CP15
help
If processor has no CP15 register, this processor ID is
used instead of the auto-probing which utilizes the register.
config REMAP_VECTORS_TO_RAM
bool 'Install vectors to the begining of RAM' if DRAM_BASE
depends on DRAM_BASE
help
The kernel needs to change the hardware exception vectors.
In nommu mode, the hardware exception vectors are normally
placed at address 0x00000000. However, this region may be
occupied by read-only memory depending on H/W design.
If the region contains read-write memory, say 'n' here.
If your CPU provides a remap facility which allows the exception
vectors to be mapped to writable memory, say 'n' here.
Otherwise, say 'y' here. In this case, the kernel will require
external support to redirect the hardware exception vectors to
the writable versions located at DRAM_BASE.
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