https://github.com/torvalds/linux
Revision a3df6f7d3090e611bcc774cd2cba45ae016d37e1 authored by Paul Mackerras on 03 September 2009, 01:52:02 UTC, committed by Ingo Molnar on 03 September 2009, 06:41:53 UTC
I had the codes for L1 D-cache load accesses and misses swapped
around, and the wrong codes for LL-cache accesses and misses.
This corrects them.

Reported-by: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: <stable@kernel.org>
LKML-Reference: <19103.8514.709300.585484@cargo.ozlabs.ibm.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
1 parent eced1df
History
Tip revision: a3df6f7d3090e611bcc774cd2cba45ae016d37e1 authored by Paul Mackerras on 03 September 2009, 01:52:02 UTC
perf_counter/powerpc: Fix cache event codes for POWER7
Tip revision: a3df6f7
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.gitignore -rw-r--r-- 952 bytes
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