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05 April 2024, 19:05:47 UTC
Revision a644b2774d41409519bb33a16bd577cb41bb3095 authored by Shinya Kuribayashi on 03 March 2009, 09:05:51 UTC, committed by Ralf Baechle on 11 March 2009, 20:11:07 UTC 
MIPS: NEC VR5500 processor support fixup
 
Current VR5500 processor support lacks of some functions which are
expected to be configured/synthesized on arch initialization.

Here're some VR5500A spec notes:

* All execution hazards are handled in hardware.

* Once VR5500A stops the operation of the pipeline by WAIT instruction,
  it could return from the standby mode only when either a reset, NMI
  request, or all enabled interrupts is/are detected.  In other words,
  if interrupts are disabled by Status.IE=0, it keeps in standby mode
  even when interrupts are internally asserted.

  Notes on WAIT: The operation of the processor is undefined if WAIT
  insn is in the branch delay slot.  The operation is also undefined
  if WAIT insn is executed when Status.EXL and Status.ERL are set to 1.

* VR5500A core only implements the Load prefetch.

With these changes, it boots fine.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1 parent c189846
History
Tip revision: a644b2774d41409519bb33a16bd577cb41bb3095 authored by Shinya Kuribayashi on 03 March 2009, 09:05:51 UTC
MIPS: NEC VR5500 processor support fixup
Tip revision: a644b27
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