https://github.com/torvalds/linux
Revision aa638cfe3e7358122a15cb1d295b622aae69e006 authored by Wei Li on 20 December 2019, 09:17:10 UTC, committed by Catalin Marinas on 20 December 2019, 17:57:22 UTC
HiSilicon Taishan v110 CPUs didn't implement CSV2 field of the
ID_AA64PFR0_EL1, but spectre-v2 is mitigated by hardware, so
whitelist the MIDR in the safe list.

Signed-off-by: Wei Li <liwei391@huawei.com>
[hanjun: re-write the commit log]
Signed-off-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
1 parent 8ae4bcf
History
Tip revision: aa638cfe3e7358122a15cb1d295b622aae69e006 authored by Wei Li on 20 December 2019, 09:17:10 UTC
arm64: cpu_errata: Add Hisilicon TSV110 to spectre-v2 safe list
Tip revision: aa638cf
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.clang-format -rw-r--r-- 15.0 KB
.cocciconfig -rw-r--r-- 59 bytes
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