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13 June 2022, 11:31:42 UTC
Revision adb3789264c4e8567113a0e764ad30ce6e8737f3 authored by Deng-Cheng Zhu on 01 April 2013, 18:14:28 UTC, committed by Ralf Baechle on 05 April 2013, 13:10:45 UTC 
MIPS: Fix ISA level which causes secondary cache init bypassing and more
 
The commit a96102be70 introduced set_isa() where compatible ISA info is
also set aside from the one gets passed in. It means, for example, 1004K
will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like
the following inappropriate:

if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
    c->isa_level == MIPS_CPU_ISA_M32R2 ||
    c->isa_level == MIPS_CPU_ISA_M64R1 ||
    c->isa_level == MIPS_CPU_ISA_M64R2)

This patch fixes it.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1 parent ed1197f
History
Tip revision: adb3789264c4e8567113a0e764ad30ce6e8737f3 authored by Deng-Cheng Zhu on 01 April 2013, 18:14:28 UTC
MIPS: Fix ISA level which causes secondary cache init bypassing and more
Tip revision: adb3789
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