https://github.com/torvalds/linux
Revision ae7a609c34b6fb12328c553b5f9aab26ae74a28e authored by John David Anglin on 25 July 2017, 21:11:26 UTC, committed by Helge Deller on 25 July 2017, 21:36:53 UTC
Helge noticed that we flush the TLB page in flush_cache_page but not in
flush_cache_range or flush_cache_mm.

For a long time, we have had random segmentation faults building
packages on machines with PA8800/8900 processors.  These machines only
support equivalent aliases.  We don't see these faults on machines that
don't require strict coherency.  So, it appears TLB speculation
sometimes leads to cache corruption on machines that require coherency.

This patch adds TLB flushes to flush_cache_range and flush_cache_mm when
coherency is required.  We only flush the TLB in flush_cache_page when
coherency is required.

The patch also optimizes flush_cache_range.  It turns out we always have
the right context to use flush_user_dcache_range_asm and
flush_user_icache_range_asm.

The patch has been tested for some time on rp3440, rp3410 and A500-44.
It's been boot tested on c8000.  No random segmentation faults were
observed during testing.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Cc: stable@vger.kernel.org # 4.9+
Signed-off-by: Helge Deller <deller@gmx.de>
1 parent 5618883
History
Tip revision: ae7a609c34b6fb12328c553b5f9aab26ae74a28e authored by John David Anglin on 25 July 2017, 21:11:26 UTC
parisc: Prevent TLB speculation on flushed pages on CPUs that only support equivalent aliases
Tip revision: ae7a609
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arch
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certs
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drivers
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include
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lib
mm
net
samples
scripts
security
sound
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usr
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.cocciconfig -rw-r--r-- 59 bytes
.get_maintainer.ignore -rw-r--r-- 31 bytes
.gitattributes -rw-r--r-- 30 bytes
.gitignore -rw-r--r-- 1.3 KB
.mailmap -rw-r--r-- 8.1 KB
COPYING -rw-r--r-- 18.3 KB
CREDITS -rw-r--r-- 96.2 KB
Kbuild -rw-r--r-- 2.2 KB
Kconfig -rw-r--r-- 252 bytes
MAINTAINERS -rw-r--r-- 411.0 KB
Makefile -rw-r--r-- 58.8 KB
README -rw-r--r-- 722 bytes

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