| b1d8a4c | Brian Viele | 20 March 2020, 22:21:38 UTC | stm32h7: added minimal stm32h7 exti defs, which share with G0. Separated definitions that did not seem consistent between the "v2" EXTI platforms. Added SYSCFG defs needed for EXTICR settings. | 23 March 2020, 13:23:21 UTC |
| 89074d6 | Brian Viele | 10 March 2020, 03:07:53 UTC | stm32h7: fix inverted VOS settings for Vcore. | 10 March 2020, 10:16:26 UTC |
| 4a11e35 | Karl Palsson | 04 March 2020, 22:32:58 UTC | stm32l1: desig: use new mechanism to support different densities Fixes: https://github.com/libopencm3/libopencm3/issues/234 uses the new mechanisms introduced to address a similar problem on F7. Tested on a medium density part (0x429) that returns the same ids as before, tested on a high density part that now _doesnt_, but that's now correct :) | 06 March 2020, 22:53:03 UTC |
| 78c23ba | Karl Palsson | 06 March 2020, 01:14:44 UTC | doc: stm32f4: fix broken groupings Now all the register value sets are in the generated output | 06 March 2020, 01:14:44 UTC |
| b146fd6 | Karl Palsson | 06 March 2020, 01:14:17 UTC | doc: stm32: flash: tidy up doxygen warnings and broken groupings | 06 March 2020, 01:14:17 UTC |
| 3df3ed7 | Karl Palsson | 06 March 2020, 01:13:22 UTC | doc: stm32f0/f3: adc: fix doxygen warnings | 06 March 2020, 01:13:22 UTC |
| dca79bf | Karl Palsson | 06 March 2020, 01:11:45 UTC | doc: stm32l1: lcd: fix groupings and convert to doxygen | 06 March 2020, 01:11:45 UTC |
| 341bd84 | Karl Palsson | 06 March 2020, 01:10:20 UTC | doc: stm32h7: cleanup warnings and groupings Move shifts and masks outside groups to clarify docs from a user point of view. fix missing or broken groupings | 06 March 2020, 01:10:20 UTC |
| 4953d67 | Brian Viele | 05 March 2020, 00:10:33 UTC | stm32h7: per comments, improved consistency with other rcc impls. Reduced the sea of enums, and renamed config parameters to match other implementations, cribbing off of the G0 config, as it is closer to the level of complexity. Updated initialization code to utilize the new values. Added flash and LDO configuration from RCC init to be more consistent with STM32 platform initialization. | 05 March 2020, 22:07:10 UTC |
| 5f8cbb9 | Karl Palsson | 05 March 2020, 21:59:29 UTC | stm32: ltdc: clarify warning on faulty include No code change. | 05 March 2020, 21:59:29 UTC |
| fb0cac4 | François Finfe | 18 February 2020, 13:25:08 UTC | stm32: adc-v2: add adc_{en,dis}able_delayed_conversion_mode To control AUTODELAY feature of the ADC. | 04 March 2020, 23:29:31 UTC |
| f1073e7 | Karl Palsson | 04 March 2020, 23:24:02 UTC | stm32h7: stop attempting to use common usart code. Until h7 implements a method of providing the periph clocks in a compatible manner, they simply can't use the common_all files. | 04 March 2020, 23:24:02 UTC |
| 2ca56f4 | Brian Viele | 17 December 2019, 07:07:55 UTC | stm32h7: updates to PWR and RCC to support PLL configuration. PLL configuration on the H7 is pretty involved, and takes a number of configurations to make it work. In order to make peripheral drivers a bit easier to implement, working with a soft clock tree in the rcc module which stores the clock settings for each clock as they are setup such that users can request the clock value from the RCC module for configuration. Added getter for the clock which allows the user to pass the base address of the peripheral, and get the peripheral clock value for convenience. Clock configuration is still missing values for setting up all of the kernel clocks for the peripherals, but this is in work, and there is a framework to do so. Have tested to 400MHz without issue. Peripherals that are explicitly supported are working and the clock tree values appear to follow correctly. Added LDO settings to allow setting the scaling to support high frequencies. | 04 March 2020, 23:17:02 UTC |
| 97688b9 | Matthew Lai | 25 September 2019, 11:47:55 UTC | stm32: desig: refactor to allow targets to have different addresses In this commit, support for the different base addresses for different F7 parts is added, but the mechanism is now in place for L1 and others. Reviewed-by: Karl Palsson <karlp@tweak.net.au> (whitespace fixed, commit msg reworded) | 04 March 2020, 22:16:31 UTC |
| f1b4a4d | Karl Palsson | 04 March 2020, 22:02:45 UTC | stm32f3: adc: consistently use unshifted and tweak teh docs a little | 04 March 2020, 22:02:45 UTC |
| 49285ed | François Finfe | 18 February 2020, 10:48:11 UTC | stm32f3: fix missing reg mask for adc_set_multi_mode Missing defines for ADC_CCR DUAL values have also been added. | 18 February 2020, 23:13:00 UTC |
| cb0661f | Brian Viele | 04 February 2020, 01:26:44 UTC | stm32h7: fmc: added bit defs for async configuration. | 16 February 2020, 13:52:04 UTC |
| 72274d3 | dima | 02 February 2020, 10:55:01 UTC | Remove SRCLIBDIR definition from the top Makefile All submakefiles have sensible defaults (either .. or ../..), so there is no need to fiddle with whitespaces in the dir name. | 02 February 2020, 10:55:01 UTC |
| d0d23cf | Jakob Haufe | 30 January 2020, 20:04:35 UTC | ld: lpc17xx: Fix RAM2_OFF on LPC17[78]x - RAM2_OFF is at 0x20004000 (see UM10470 page 15) - 0x20040000 is not a valid address on LPC17[78]x | 31 January 2020, 20:52:12 UTC |
| 4b3d583 | Caleb Szalacinski | 29 January 2020, 05:53:55 UTC | swm050: register fix for timer_clock_div | 29 January 2020, 05:53:55 UTC |
| 8a915a8 | Karl Palsson | 28 January 2020, 23:04:30 UTC | doc: sam: fix duplicate and missing parameter docs | 28 January 2020, 23:04:30 UTC |
| 4f2d6c2 | Karl Palsson | 28 January 2020, 23:04:00 UTC | doc: enable samd and sam4l family documentation Was lost in some re-org, turn it back on. | 28 January 2020, 23:04:00 UTC |
| 7da29d3 | Karl Palsson | 28 January 2020, 23:03:39 UTC | stm32: desig: doc: merge duplicate documentation sections Use the best one. | 28 January 2020, 23:03:39 UTC |
| 8c37e5c | Karl Palsson | 28 January 2020, 22:41:14 UTC | stm32: crc: merge duplicate documentation Avoids warnings from doxygen. Leaves it purely in the headers so it's accessible in code completion as well. | 28 January 2020, 22:41:14 UTC |
| 6f25d51 | Karl Palsson | 28 January 2020, 22:30:39 UTC | cm3: nvic: use separate documentation to avoid warnings on cm0 Squelches some doxygen warnings, and makes the generated docs "right" for each arch | 28 January 2020, 22:31:38 UTC |
| 26d6f8f | Karl Palsson | 28 January 2020, 22:07:27 UTC | swm050: timer: use more standard bit definitions We normally use periph_reg_field naming, and most of this file was already consistent. Switch the stragglers. | 28 January 2020, 22:31:38 UTC |
| a6aecf8 | Karl Palsson | 28 January 2020, 21:50:00 UTC | swm050: simplify doxygen We don't need groupings around each enum, they format nicely into a section already. Likewise, the doxygen _is_ documentation, so we don't need extra versions of it in places. Also fix a few warnings generated. | 28 January 2020, 22:31:24 UTC |
| f06a1ca | Caleb Szalacinski | 06 January 2020, 02:12:15 UTC | SWM050: Adds the timer peripheral and updates the README. | 28 January 2020, 20:58:50 UTC |
| 7daa6f1 | Fabio Pugliese Ornellas | 11 January 2020, 22:02:50 UTC | usb: define USB_CLASS_DFU | 12 January 2020, 20:31:26 UTC |
| a8a92b4 | Guillaume Revaillot | 05 February 2019, 16:22:55 UTC | rng: fix clock error handling, based on RM. According to L4/L0/G0 RM, in case of clock error, interrupt flag must be cleared, and CECS flag should be cleared as soon as clock meets requirement. Reviewed-on: https://github.com/libopencm3/libopencm3/pull/1062 | 05 January 2020, 00:25:12 UTC |
| 5866852 | Guillaume Revaillot | 05 February 2019, 16:17:34 UTC | rng: handle noise source / seed error. If noise source error occurs, flag must be cleared and data register must be discarded (at least 12 reads to flush pipeline on G0). Other device mention start/restart of chip, so, do both (better safe than sorry). Reviewed-on: https://github.com/libopencm3/libopencm3/pull/1062 | 05 January 2020, 00:25:00 UTC |
| 5a53f18 | Guillaume Revaillot | 05 February 2019, 13:35:18 UTC | rng: check error before checking if data ready. mostly cosmetic, but ease debugging. | 05 January 2020, 00:24:43 UTC |
| 64baacf | Guillaume Revaillot | 05 February 2019, 13:34:08 UTC | rng: add irq enable/disable helper. | 05 January 2020, 00:24:43 UTC |
| e2ac1a6 | Jacob Walser | 25 September 2019, 02:35:54 UTC | stm32f3: bugfix + adjust wwdg threshold signatures to support 12 bit resolution - these registers are 12 bits wide - bugfix clearing thresholds so that both upper and lower thresholds can be configured on the **window** watchdog | 05 January 2020, 00:10:12 UTC |
| a759a0d | Jacob Walser | 25 September 2019, 02:16:33 UTC | stm32f3: unify implementation with f0 adc_enable_analog_watchdog_on_selected_channel - match the same logic as the f0 api - use ADC_CFGR1_AWD1CH_VAL macro to mask the channel bits - don't check if channel is < 18q - enable the awd in addition to setting the selection to single channel monitoring (in following with the signature and @brief 'enable' | 05 January 2020, 00:10:01 UTC |
| 854da96 | Jacob Walser | 24 September 2019, 04:02:39 UTC | stm32f0: adjust wwdg threshold signatures to support 12 bit resolution | 05 January 2020, 00:08:48 UTC |
| 5409ce7 | Jacob Walser | 24 September 2019, 04:00:57 UTC | adc_common_v2: bugfix ADC_xT1_VAL(x) mask out bits that must not be written | 05 January 2020, 00:08:48 UTC |
| 6fc1ff2 | balanceTWK | 10 September 2019, 12:22:03 UTC | stm32:L4:flash: support erasing pages on bank 2 Reviewed-by: Karl Palsson <karlp@tweak.net.au> (fixed code style) | 05 January 2020, 00:03:06 UTC |
| d44ffe8 | Brian Cooke | 17 November 2019, 01:30:13 UTC | tests/gadget0: avoid floating point division Reviewed-by: Karl Palsson <karlp@tweak.net.au> (Changed from cast to literal int, more inline with efm32 and clearer intent) | 04 January 2020, 23:49:16 UTC |
| 18f4d7c | Karl Palsson | 04 January 2020, 23:13:08 UTC | stm32f3: rtc: include correct shared header rtc_common_all never existed, and f3 has the same "v2" peripheral used by ~all parts other than the f1. We don't have any f3 rtc test code, but the existing code was clearly wrong, and this is at least including the correct basic defines. Fixes: https://github.com/libopencm3/libopencm3/issues/1106 | 04 January 2020, 23:13:08 UTC |
| 911d4be | Karl Palsson | 04 January 2020, 23:01:57 UTC | gitignore: ensure some non-generated are included A normal git clone doesn't catch these, as it _knows_ that the files are in the git repo and should be tracked. However, downloading a tarball, and adding it to a new git repo shows up the problem as important files are simply not added, and would be dropped by git clean. Reported-by: https://github.com/libopencm3/libopencm3/issues/1153 | 04 January 2020, 23:01:57 UTC |
| 9d15ac7 | Guillaume Revaillot | 16 October 2019, 14:48:09 UTC | cortex: FAULTMASK does not exist on armv6m. | 04 January 2020, 21:53:34 UTC |
| db6237c | Guillaume Revaillot | 30 December 2019, 17:50:18 UTC | stm32: extract g0 exti stuff to exti_common_v2. stm32l5 basically uses the same stuff. | 01 January 2020, 18:47:13 UTC |
| f7a952c | Sam Protsenko | 15 December 2019, 21:03:53 UTC | stm32: Fix typo in RCC related comments ABP -> APB Signed-off-by: Sam Protsenko <joe.skb7@gmail.com> | 26 December 2019, 13:46:30 UTC |
| df15b26 | Karl Palsson | 25 December 2019, 21:04:17 UTC | usb: hid: add a stub file for doxygen Unlike with the doxygen source generation, we can't autoguess which of the class files are eligible automatically. Instead, make a stub hid file, (which we can now start adding to, if desired) and include it in all builds that include other class stubs. | 25 December 2019, 21:04:17 UTC |
| f2f5083 | Fabio Pugliese Ornellas | 09 November 2019, 20:32:13 UTC | usb: Add more HID Class constants | 25 December 2019, 20:44:46 UTC |
| aabd4da | Karl Palsson | 25 December 2019, 20:43:02 UTC | stm32g0: syscfg: doc: fix missing grouping | 25 December 2019, 20:43:02 UTC |
| 87dbf40 | Guillaume Revaillot | 28 August 2019, 16:04:02 UTC | stm32g0: rcc: group rcc_registers and registers values | 25 December 2019, 20:34:11 UTC |
| f70f0d0 | Guillaume Revaillot | 03 July 2019, 14:00:13 UTC | stm32g0: pwr: doc: remove duplicated ingroup | 25 December 2019, 20:34:11 UTC |
| 48afe3c | Guillaume Revaillot | 17 September 2019, 17:00:31 UTC | stm32g0: flash: fix wrong comment. | 25 December 2019, 20:34:11 UTC |
| ebd265c | Guillaume Revaillot | 06 September 2019, 16:01:35 UTC | stm32g0: rng: typo in header. | 25 December 2019, 20:34:11 UTC |
| 169d235 | Guillaume Revaillot | 08 November 2019, 15:23:18 UTC | stm32: lptimer: fix documentation | 25 December 2019, 20:34:11 UTC |
| 070058f | Guillaume Revaillot | 08 November 2019, 14:24:53 UTC | stm32: adc: doc fix declare chselr group in v2 single header, where adc_chselr reg is declared | 25 December 2019, 20:34:11 UTC |
| e7c8f18 | Guillaume Revaillot | 08 November 2019, 13:47:11 UTC | stm32: adc: group adc_registers | 25 December 2019, 20:34:11 UTC |
| 86b4cf6 | Karl Palsson | 25 December 2019, 20:30:17 UTC | stm32h7: fix typo in doxygen description | 25 December 2019, 20:30:17 UTC |
| a5b6673 | Karl Palsson | 25 December 2019, 20:30:03 UTC | stm32: usart-v2: fix some doxygen linking problems | 25 December 2019, 20:30:03 UTC |
| aabefea | Brian Viele | 12 December 2019, 01:07:49 UTC | stm32h7: usart: support new fifo features Supported by H7 and G4 varieties at present. | 25 December 2019, 20:29:24 UTC |
| fa3c1df | Karl Palsson | 25 December 2019, 13:43:03 UTC | pac55xx: fix up and simplify some doxygen | 25 December 2019, 13:44:49 UTC |
| a3406f1 | Brian Viele | 02 December 2019, 02:46:07 UTC | pac55xx: gpio: Initial Implementation of PAC55xx GPIO Driver * Conforms mostly to the STM32 GPIO API where possible. * Supports pin configuration (direction, pull-up/down, etc.) as well as pinmux configuration. * Supports set/clear/get operations to the GPIO port/pins. * Created base doxy header and groups to align with existing formatting. | 25 December 2019, 13:44:35 UTC |
| 9598b7f | Karl Palsson | 12 December 2019, 20:37:58 UTC | doc: stm32:rcc: flag "better" periph enable options The original rcc_peripheral_enable_clock aren't explicitly deprecated, as they do let you enable multiple periphs in one call. But they're error prone, from user feedback, so update the docs to ensure people know what the other options are. | 12 December 2019, 20:37:58 UTC |
| 85275fd | Karl Palsson | 12 December 2019, 20:36:51 UTC | stm32f1: adc: doc: drop undocumented examples There's already example code, this was just conflicting extra code that wasn't being included in doxygen anyway. | 12 December 2019, 20:36:51 UTC |
| 557e7aa | Karl Palsson | 12 December 2019, 20:35:57 UTC | doc: avoid usage of rcc_peripheral_enable_clock Use the simpler, safer rcc_periph_clock_enable instead | 12 December 2019, 20:35:57 UTC |
| 4a9ba30 | TomasPech | 11 December 2019, 23:32:00 UTC | stm32f4: rcc_clock_setup_pll() correctly enable PWR Original code used the special macros for rcc_periph_clock_enable instead of the appropraite APB1ENR bit definition. Switch to the correct, simpler form, using the correct parameter. | 12 December 2019, 20:12:27 UTC |
| 3c34f00 | Darrell Harmon | 10 December 2019, 20:33:49 UTC | genlink: avoid creating blank linker script if gcc fails When piping to a file, if arm-none-eabi-gcc is not present in the path, a blank linker script is created with genlink. After sourcing a bash script to add GCC to the path, the linker script doesn't get rebuilt due to a fresh timestamp despite failing to generate. | 11 December 2019, 09:42:05 UTC |
| 9af9a1d | Mathias Nord | 03 December 2019, 13:45:47 UTC | stm32g0: use spi v2 | 03 December 2019, 13:45:47 UTC |
| 867e382 | Karl Palsson | 28 November 2019, 22:25:36 UTC | readme: add h7 and g0 | 28 November 2019, 22:25:36 UTC |
| af384db | Karl Palsson | 28 November 2019, 22:16:54 UTC | doc: fix some broken groups uncovered while reviewing h7 code | 28 November 2019, 22:16:54 UTC |
| af8a177 | Karl Palsson | 28 November 2019, 22:16:34 UTC | stm32h7: doc: fix some missing group definitions | 28 November 2019, 22:16:34 UTC |
| 5330243 | Brian Viele | 07 November 2019, 02:32:54 UTC | stm32h7: Initial introduction into libopencm3. Updates to a base set of includes to map to the h7 include files which are mainly based on the f7 versions for simple devices (e.g. SPI, USART, GPIO). Custom files that have been implemented from the datasheet/ref manual include the memory map, RCC, PWR definitions, and irq.json file for generation of nvic files for interrupt mapping. Additional functionality, especially PLL and tweaks for non-F7 compatible implementations coming in future commits. Added documentation tree configuration. Reviewed-by: Karl Palsson <karlp@tweak.net.au> Changed dmaX_streamX to dmaX_strX in a few places for consistency | 28 November 2019, 22:15:24 UTC |
| da0c6a6 | Karl Palsson | 28 November 2019, 11:43:01 UTC | swm050: wdt: doxygen polish | 28 November 2019, 11:43:01 UTC |
| 47b59e2 | Caleb Szalacinski | 27 October 2019, 20:12:09 UTC | swm050: Adds WDT peripheral Reviewed-by: Karl Palsson <karlp@tweak.net.au> (Fixed an &| in wdt_set_time) | 28 November 2019, 11:42:31 UTC |
| dd18b9f | Brian Viele | 26 November 2019, 19:18:37 UTC | Qorvo pac55xx: initial support Qorvo (Nee Active Semi) PAC55xx "Intelligent Motor Control" parts, cortex-m4 SoCs | 26 November 2019, 23:28:02 UTC |
| bcfdcc0 | Guillaume Revaillot | 31 January 2019, 14:43:24 UTC | stm32g0: add syscfg header. | 25 November 2019, 20:49:20 UTC |
| 0a68b01 | larchuto | 21 November 2019, 17:59:32 UTC | stm32l4: Fix typo impacting uart4 and uart5 | 21 November 2019, 17:59:32 UTC |
| 38b45c8 | Guillaume Revaillot | 21 January 2019, 14:36:49 UTC | stm32g0: add adc. v2 "single" peripheral with a couple of tweaks : - added registers to configure two additionnal advanced analog watchdog. - different adc sampling time time based on channel groups. - 8 steps adc sequence injection, using chselr/chselrmode. And a note on the rm explaining that after every configuration change to ADC_CFGR1's SCANDIR or CHSELRMOD or CHSELR register, user need to check that configuration is applied before any other modification / adc conversion start.. making adc_set_reqular a bit painfull to read.. | 08 November 2019, 14:19:17 UTC |
| a34da53 | Guillaume Revaillot | 12 June 2019, 09:52:04 UTC | stm32g0: add dmamux DMAMUX peripheral is a dma request router/trigger, present on g0, wb, h7 and l4+. Basically it allows to easily map peripheral requests to whatever dma channel we want to use (similarily to the DMA_CSELR register, but without limitation) but, it also also adds some clever dma request synchronization and even some dma request generation logic via internal request generator "channels", allowing some requests chaining, or triggering reqs from non dma capable peripherals. nb: g0 only features 1 dmamux bloc, supports 7 irq and 4 generators, l4+ supports 13 dma channels and 3 generators and h7 has two dmamuxes, with support for the 15 dma channels and 7 generators - so as much CxCR and RGxCR register - but they are bit to bit compatible - excluding of course the sync/sig and dma requests id mappings. btw, currently, request generator channels are defined in common header, but maybe we should define them in device header ? or we dont care (like for dma channels, only defined in dma_f24 but not for other devices ?). See ST AN5224 for more information | 08 November 2019, 12:47:41 UTC |
| b9f183b | Guillaume Revaillot | 31 January 2019, 17:31:23 UTC | stm32g0: add dma. same same, bit for bit, except not ;) - Channel request mapping now depends on a new DMAMUX peripheral, and there's no default preset. So, before enabling dma channel after its configuration, request must be configured by : dmamux_set_dma_channel_request(DMAMUX1, DMA_CHANNELx, request_number_from_datasheet); | 08 November 2019, 12:47:41 UTC |
| 7a27397 | Karl Palsson | 06 November 2019, 19:44:41 UTC | stm32: rtcv2: don't shift the "month tens" bit None of the other masks are shifted, don't shift this field either. Fixes: https://github.com/libopencm3/libopencm3/issues/1123 | 06 November 2019, 19:45:20 UTC |
| 6d91399 | Karl Palsson | 22 October 2019, 10:35:04 UTC | devices.data: add some more l0 parts | 22 October 2019, 10:35:04 UTC |
| 88b32e3 | Karl Palsson | 22 October 2019, 10:23:18 UTC | devices.data: stm32f4: add all missing parts | 22 October 2019, 10:23:18 UTC |
| af05098 | Eivind Alexander Bergem | 22 October 2019, 07:04:53 UTC | devices.data: Added stm32f410 | 22 October 2019, 07:04:53 UTC |
| 2b54119 | Karl Palsson | 18 October 2019, 22:38:16 UTC | cm3: scs: drop all duplicate information Keeps the best version of the documentation. Fixes: https://github.com/libopencm3/libopencm3/pull/269 | 18 October 2019, 22:38:16 UTC |
| 833da4b | Karl Palsson | 18 October 2019, 22:33:23 UTC | cm3: extract SCB SHPR to the SCB world it belongs to Pull out the duplicate into the right file, keeping the newly fixed version. | 18 October 2019, 22:33:23 UTC |
| 3ebd71b | Karl Palsson | 18 October 2019, 22:29:13 UTC | cm3: extract Coresight LSR/LAR definitions Use a single point of definition for the offset, and add it where it was missing. | 18 October 2019, 22:29:13 UTC |
| d8579dd | Matt Anderson | 19 June 2019, 08:01:37 UTC | CortexM0: IPR and SHPR are only word addressable For ARMv6M, the IPR and SHPR registers are accessible only when adddressed with a 32bit word read or write. Currently in libopencm3 all NVIC interrupt priority register accesses are made using an 8bit read or write, which results in the hardware ignoring the write or always returning 0 on read. Address this by introducing NVIC_IPR32() and SCS_SHPR32() macro and conditional implementation of nvic_set_priority when building for cortex-m0. See ARMv6M developer documentation: IPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/Cihgjeed.html SHPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CIAGECDD.html | 17 October 2019, 21:26:13 UTC |
| baa2f13 | Karl Palsson | 17 October 2019, 11:41:02 UTC | swm050: doc: tweak peripheral apis groupings Makes it more consistent with the other families. | 17 October 2019, 11:41:55 UTC |
| 3c4ee6f | Caleb Szalacinski | 21 September 2019, 20:43:50 UTC | SWM050: Finishes GPIO, IAP flash, sysclock, sleep/stop, and the sysctl memory map. Updates the main memory map and the makefile. Adds the SWM050 to devices.data, so that a linker script can be automatically generated. Reviewed-by: Karl Palsson <karlp@tweak.net.au> | 17 October 2019, 11:41:33 UTC |
| 1fbfdec | Bryan PEREIRA | 16 October 2019, 09:06:41 UTC | stm32f3: Add SPI4 BASE | 16 October 2019, 14:41:00 UTC |
| 77d96a3 | Nicholas Rossomando | 12 October 2019, 06:02:23 UTC | stm32l0: crc: enable common code | 12 October 2019, 14:11:39 UTC |
| b5d66ee | Karl Palsson | 03 October 2019, 11:37:47 UTC | devices.data: add all missing stm32f3 parts Filled missing variants, added missing families, corrected one or two mistakes in ccm availability Fixes: https://github.com/libopencm3/libopencm3/pull/1109 | 03 October 2019, 11:37:47 UTC |
| 66e6a20 | Karl Palsson | 30 September 2019, 10:28:21 UTC | doc: stm32f1: gpio: remove redundant doxygen types Fixes https://github.com/libopencm3/libopencm3/issues/1108 | 30 September 2019, 10:28:21 UTC |
| ec2d964 | Jonathan Halmen | 27 July 2019, 17:29:47 UTC | stm32f4: rcc: add plli2s config function | 27 September 2019, 13:55:56 UTC |
| 203d0ca | Jonathan Halmen | 27 July 2019, 17:09:43 UTC | stm32f4: rcc: remove unnecessary pllsai functions existing standard functions for these are * rcc_osc_on(RCC_PLLSAI); * rcc_is_osc_ready(RCC_PLLSAI); | 27 September 2019, 13:43:06 UTC |
| 5fbe5c8 | Matthew Lai | 22 September 2019, 00:39:49 UTC | devices.data: Added STM32F7 value line devices with 64K flash | 23 September 2019, 22:45:36 UTC |
| b0c3de8 | Karl Palsson | 03 September 2019, 22:23:26 UTC | devices.data: add missing stm32f301 parts Fixes: https://github.com/libopencm3/libopencm3/issues/1098 | 03 September 2019, 22:23:26 UTC |
| 8a1cfa8 | Guillaume Revaillot | 28 August 2019, 16:04:02 UTC | stm32g0: use proper register for gpio peripheral clock sleep enable. Reviewed-by: Karl Palsson <karlp@tweak.net.au> | 28 August 2019, 20:54:35 UTC |
| 998e647 | Guillaume Revaillot | 28 August 2019, 10:03:55 UTC | stm32g0: memorymap: get rid of apb1/apb2 reference, device only has one apb. I apparently based memorymap.h on previously written header without noticing that g0 has only one apb despite a big hole in the memory space and addresses matching usual apb1/apb2 split.. | 28 August 2019, 10:03:55 UTC |
| 1928e6e | Guillaume Revaillot | 27 August 2019, 14:44:45 UTC | doc: typo | 28 August 2019, 01:41:14 UTC |
| 562dca7 | Guillaume Revaillot | 27 August 2019, 13:18:44 UTC | stm32f4: doc: f4 are cortex m4f based | 28 August 2019, 01:41:14 UTC |
| ec59779 | Guillaume Revaillot | 27 August 2019, 14:23:54 UTC | stm32g0: fix bad typos in memorymap, impacting tim1 and tim15-17. | 27 August 2019, 14:24:42 UTC |
