https://github.com/torvalds/linux
Revision b2d7a075a1ccef2fb321d595802190c8e9b39004 authored by Juergen Gross on 21 August 2018, 15:37:55 UTC, committed by Boris Ostrovsky on 27 August 2018, 18:20:49 UTC
Using only 32-bit writes for the pte will result in an intermediate L1TF vulnerable PTE. When running as a Xen PV guest this will at once switch the guest to shadow mode resulting in a loss of performance. Use arch_atomic64_xchg() instead which will perform the requested operation atomically with all 64 bits. Some performance considerations according to: https://software.intel.com/sites/default/files/managed/ad/dc/Intel-Xeon-Scalable-Processor-throughput-latency.pdf The main number should be the latency, as there is no tight loop around native_ptep_get_and_clear(). "lock cmpxchg8b" has a latency of 20 cycles, while "lock xchg" (with a memory operand) isn't mentioned in that document. "lock xadd" (with xadd having 3 cycles less latency than xchg) has a latency of 11, so we can assume a latency of 14 for "lock xchg". Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jan Beulich <jbeulich@suse.com> Tested-by: Jason Andryuk <jandryuk@gmail.com> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
1 parent f7c90c2
Tip revision: b2d7a075a1ccef2fb321d595802190c8e9b39004 authored by Juergen Gross on 21 August 2018, 15:37:55 UTC
x86/pae: use 64 bit atomic xchg function in native_ptep_get_and_clear
x86/pae: use 64 bit atomic xchg function in native_ptep_get_and_clear
Tip revision: b2d7a07
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| .cocciconfig | -rw-r--r-- | 59 bytes |
| .get_maintainer.ignore | -rw-r--r-- | 31 bytes |
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| COPYING | -rw-r--r-- | 423 bytes |
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| Makefile | -rw-r--r-- | 58.5 KB |
| README | -rw-r--r-- | 800 bytes |
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