Revision b5ad2c21934951bbf6aadd8adbdd9889baad0ac0 authored by Markos Chandras on 15 January 2015, 10:28:29 UTC, committed by Markos Chandras on 17 February 2015, 15:37:31 UTC
The secondary cache initialization and configuration code is processor specific so we need to handle MIPS R6 cores as well. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
1 parent 4ee4862
| File | Mode | Size |
|---|---|---|
| check-all.sh | -rw-r--r-- | 433 bytes |
| rt-tester.py | -rwxr-xr-x | 5.2 KB |
| t2-l1-2rt-sameprio.tst | -rw-r--r-- | 1.5 KB |
| t2-l1-pi.tst | -rw-r--r-- | 1.2 KB |
| t2-l1-signal.tst | -rw-r--r-- | 1.2 KB |
| t2-l2-2rt-deadlock.tst | -rw-r--r-- | 1.3 KB |
| t3-l1-pi-1rt.tst | -rw-r--r-- | 1.4 KB |
| t3-l1-pi-2rt.tst | -rw-r--r-- | 1.4 KB |
| t3-l1-pi-3rt.tst | -rw-r--r-- | 1.4 KB |
| t3-l1-pi-signal.tst | -rw-r--r-- | 1.5 KB |
| t3-l1-pi-steal.tst | -rw-r--r-- | 1.6 KB |
| t3-l2-pi.tst | -rw-r--r-- | 1.4 KB |
| t4-l2-pi-deboost.tst | -rw-r--r-- | 2.0 KB |
| t5-l4-pi-boost-deboost-setsched.tst | -rw-r--r-- | 2.9 KB |
| t5-l4-pi-boost-deboost.tst | -rw-r--r-- | 2.2 KB |
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