Revision b5ad2c21934951bbf6aadd8adbdd9889baad0ac0 authored by Markos Chandras on 15 January 2015, 10:28:29 UTC, committed by Markos Chandras on 17 February 2015, 15:37:31 UTC
The secondary cache initialization and configuration code is processor specific so we need to handle MIPS R6 cores as well. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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