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Revision b5ad2c21934951bbf6aadd8adbdd9889baad0ac0 authored by Markos Chandras on 15 January 2015, 10:28:29 UTC, committed by Markos Chandras on 17 February 2015, 15:37:31 UTC 
MIPS: mm: scache: Add secondary cache support for MIPS R6 cores
 
The secondary cache initialization and configuration code is processor
specific so we need to handle MIPS R6 cores as well.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
1 parent 4ee4862
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draw_functrace.py -rwxr-xr-x 3.5 KB
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