Revision b89de436ff63218d31122b2176f7785b0628b3c6 authored by Edgar E. Iglesias on 02 November 2018, 13:19:12 UTC, committed by Peter Maydell on 02 November 2018, 14:10:53 UTC
Add a model of Xilinx Versal SoC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181102131913.1535-2-edgar.iglesias@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
1 parent 0f8d06f
| File | Mode | Size |
|---|---|---|
| Makefile.objs | -rw-r--r-- | 146 bytes |
| pr-helper.h | -rw-r--r-- | 1.5 KB |
| pr-manager-helper.c | -rw-r--r-- | 9.0 KB |
| pr-manager-stub.c | -rw-r--r-- | 661 bytes |
| pr-manager.c | -rw-r--r-- | 3.8 KB |
| qemu-pr-helper.c | -rw-r--r-- | 29.6 KB |
| trace-events | -rw-r--r-- | 210 bytes |
| utils.c | -rw-r--r-- | 17.9 KB |
Computing file changes ...
