Revision b90d72a6bfdb5e5c62cd223a8cdf4045bfbcb94d authored by Will Deacon on 12 January 2021, 22:18:55 UTC, committed by Catalin Marinas on 13 January 2021, 15:08:41 UTC
This reverts commit 367c820ef08082e68df8a3bc12e62393af21e4b5. lockup_detector_init() makes heavy use of per-cpu variables and must be called with preemption disabled. Usually, it's handled early during boot in kernel_init_freeable(), before SMP has been initialised. Since we do not know whether or not our PMU interrupt can be signalled as an NMI until considerably later in the boot process, the Arm PMU driver attempts to re-initialise the lockup detector off the back of a device_initcall(). Unfortunately, this is called from preemptible context and results in the following splat: | BUG: using smp_processor_id() in preemptible [00000000] code: swapper/0/1 | caller is debug_smp_processor_id+0x20/0x2c | CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.10.0+ #276 | Hardware name: linux,dummy-virt (DT) | Call trace: | dump_backtrace+0x0/0x3c0 | show_stack+0x20/0x6c | dump_stack+0x2f0/0x42c | check_preemption_disabled+0x1cc/0x1dc | debug_smp_processor_id+0x20/0x2c | hardlockup_detector_event_create+0x34/0x18c | hardlockup_detector_perf_init+0x2c/0x134 | watchdog_nmi_probe+0x18/0x24 | lockup_detector_init+0x44/0xa8 | armv8_pmu_driver_init+0x54/0x78 | do_one_initcall+0x184/0x43c | kernel_init_freeable+0x368/0x380 | kernel_init+0x1c/0x1cc | ret_from_fork+0x10/0x30 Rather than bodge this with raw_smp_processor_id() or randomly disabling preemption, simply revert the culprit for now until we figure out how to do this properly. Reported-by: Lecopzer Chen <lecopzer.chen@mediatek.com> Signed-off-by: Will Deacon <will@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Cc: Sumit Garg <sumit.garg@linaro.org> Cc: Alexandru Elisei <alexandru.elisei@arm.com> Link: https://lore.kernel.org/r/20201221162249.3119-1-lecopzer.chen@mediatek.com Link: https://lore.kernel.org/r/20210112221855.10666-1-will@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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wm8904.h
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Platform data for WM8904
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*/
#ifndef __MFD_WM8994_PDATA_H__
#define __MFD_WM8994_PDATA_H__
/* Used to enable configuration of a GPIO to all zeros */
#define WM8904_GPIO_NO_CONFIG 0x8000
/*
* R6 (0x06) - Mic Bias Control 0
*/
#define WM8904_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */
#define WM8904_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */
#define WM8904_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */
#define WM8904_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
#define WM8904_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */
#define WM8904_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */
#define WM8904_MICDET_ENA 0x0002 /* MICDET_ENA */
#define WM8904_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
#define WM8904_MICDET_ENA_SHIFT 1 /* MICDET_ENA */
#define WM8904_MICDET_ENA_WIDTH 1 /* MICDET_ENA */
#define WM8904_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
#define WM8904_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
#define WM8904_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
#define WM8904_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */
/*
* R7 (0x07) - Mic Bias Control 1
*/
#define WM8904_MIC_DET_FILTER_ENA 0x8000 /* MIC_DET_FILTER_ENA */
#define WM8904_MIC_DET_FILTER_ENA_MASK 0x8000 /* MIC_DET_FILTER_ENA */
#define WM8904_MIC_DET_FILTER_ENA_SHIFT 15 /* MIC_DET_FILTER_ENA */
#define WM8904_MIC_DET_FILTER_ENA_WIDTH 1 /* MIC_DET_FILTER_ENA */
#define WM8904_MIC_SHORT_FILTER_ENA 0x4000 /* MIC_SHORT_FILTER_ENA */
#define WM8904_MIC_SHORT_FILTER_ENA_MASK 0x4000 /* MIC_SHORT_FILTER_ENA */
#define WM8904_MIC_SHORT_FILTER_ENA_SHIFT 14 /* MIC_SHORT_FILTER_ENA */
#define WM8904_MIC_SHORT_FILTER_ENA_WIDTH 1 /* MIC_SHORT_FILTER_ENA */
#define WM8904_MICBIAS_SEL_MASK 0x0007 /* MICBIAS_SEL - [2:0] */
#define WM8904_MICBIAS_SEL_SHIFT 0 /* MICBIAS_SEL - [2:0] */
#define WM8904_MICBIAS_SEL_WIDTH 3 /* MICBIAS_SEL - [2:0] */
/*
* R121 (0x79) - GPIO Control 1
*/
#define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */
#define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
#define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
#define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
#define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */
#define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
#define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
#define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
#define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
#define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
#define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
/*
* R122 (0x7A) - GPIO Control 2
*/
#define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */
#define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */
#define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */
#define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
#define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */
#define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */
#define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */
#define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
#define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */
#define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */
#define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */
/*
* R123 (0x7B) - GPIO Control 3
*/
#define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */
#define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
#define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
#define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
#define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */
#define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
#define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
#define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
#define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
#define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
#define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
/*
* R124 (0x7C) - GPIO Control 4
*/
#define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */
#define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */
#define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */
#define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
#define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */
#define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */
#define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */
#define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
#define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */
#define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */
#define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */
#define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */
#define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */
#define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */
#define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */
#define WM8904_MIC_REGS 2
#define WM8904_GPIO_REGS 4
#define WM8904_DRC_REGS 4
#define WM8904_EQ_REGS 24
/**
* DRC configurations are specified with a label and a set of register
* values to write (the enable bits will be ignored). At runtime an
* enumerated control will be presented for each DRC block allowing
* the user to choose the configuration to use.
*
* Configurations may be generated by hand or by using the DRC control
* panel provided by the WISCE - see http://www.wolfsonmicro.com/wisce/
* for details.
*/
struct wm8904_drc_cfg {
const char *name;
u16 regs[WM8904_DRC_REGS];
};
/**
* ReTune Mobile configurations are specified with a label, sample
* rate and set of values to write (the enable bits will be ignored).
*
* Configurations are expected to be generated using the ReTune Mobile
* control panel in WISCE - see http://www.wolfsonmicro.com/wisce/
*/
struct wm8904_retune_mobile_cfg {
const char *name;
unsigned int rate;
u16 regs[WM8904_EQ_REGS];
};
struct wm8904_pdata {
int num_drc_cfgs;
struct wm8904_drc_cfg *drc_cfgs;
int num_retune_mobile_cfgs;
struct wm8904_retune_mobile_cfg *retune_mobile_cfgs;
u32 gpio_cfg[WM8904_GPIO_REGS];
u32 mic_cfg[WM8904_MIC_REGS];
};
#endif
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