Skip to main content

Browse the archive

Revision b90d72a6bfdb5e5c62cd223a8cdf4045bfbcb94d authored by Will Deacon on 12 January 2021, 22:18:55 UTC, committed by Catalin Marinas on 13 January 2021, 15:08:41 UTC 
Revert "arm64: Enable perf events based hard lockup detector"
 
This reverts commit 367c820ef08082e68df8a3bc12e62393af21e4b5.

lockup_detector_init() makes heavy use of per-cpu variables and must be
called with preemption disabled. Usually, it's handled early during boot
in kernel_init_freeable(), before SMP has been initialised.

Since we do not know whether or not our PMU interrupt can be signalled
as an NMI until considerably later in the boot process, the Arm PMU
driver attempts to re-initialise the lockup detector off the back of a
device_initcall(). Unfortunately, this is called from preemptible
context and results in the following splat:

  | BUG: using smp_processor_id() in preemptible [00000000] code: swapper/0/1
  | caller is debug_smp_processor_id+0x20/0x2c
  | CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.10.0+ #276
  | Hardware name: linux,dummy-virt (DT)
  | Call trace:
  |   dump_backtrace+0x0/0x3c0
  |   show_stack+0x20/0x6c
  |   dump_stack+0x2f0/0x42c
  |   check_preemption_disabled+0x1cc/0x1dc
  |   debug_smp_processor_id+0x20/0x2c
  |   hardlockup_detector_event_create+0x34/0x18c
  |   hardlockup_detector_perf_init+0x2c/0x134
  |   watchdog_nmi_probe+0x18/0x24
  |   lockup_detector_init+0x44/0xa8
  |   armv8_pmu_driver_init+0x54/0x78
  |   do_one_initcall+0x184/0x43c
  |   kernel_init_freeable+0x368/0x380
  |   kernel_init+0x1c/0x1cc
  |   ret_from_fork+0x10/0x30

Rather than bodge this with raw_smp_processor_id() or randomly disabling
preemption, simply revert the culprit for now until we figure out how to
do this properly.

Reported-by: Lecopzer Chen <lecopzer.chen@mediatek.com>
Signed-off-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>
Link: https://lore.kernel.org/r/20201221162249.3119-1-lecopzer.chen@mediatek.com
Link: https://lore.kernel.org/r/20210112221855.10666-1-will@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
1 parent df06824
Raw File
pmagb-b-fb.h 
/*
 *	linux/include/video/pmagb-b-fb.h
 *
 *	TURBOchannel PMAGB-B Smart Frame Buffer (SFB) card support,
 *	Copyright (C) 1999, 2000, 2001 by
 *	Michael Engel <engel@unix-ag.org> and
 *	Karsten Merker <merker@linuxtag.org>
 *	Copyright (c) 2005  Maciej W. Rozycki
 *
 *	This file is subject to the terms and conditions of the GNU General
 *	Public License.  See the file COPYING in the main directory of this
 *	archive for more details.
 */

/* IOmem resource offsets.  */
#define PMAGB_B_ROM		0x000000	/* REX option ROM */
#define PMAGB_B_SFB		0x100000	/* SFB ASIC */
#define PMAGB_B_GP0		0x140000	/* general purpose output 0 */
#define PMAGB_B_GP1		0x180000	/* general purpose output 1 */
#define PMAGB_B_BT459		0x1c0000	/* Bt459 RAMDAC */
#define PMAGB_B_FBMEM		0x200000	/* frame buffer */
#define PMAGB_B_SIZE		0x400000	/* address space size */

/* IOmem register offsets.  */
#define SFB_REG_VID_HOR		0x64		/* video horizontal setup */
#define SFB_REG_VID_VER		0x68		/* video vertical setup */
#define SFB_REG_VID_BASE	0x6c		/* video base address */
#define SFB_REG_TCCLK_COUNT	0x78		/* TURBOchannel clock count */
#define SFB_REG_VIDCLK_COUNT	0x7c		/* video clock count */

/* Video horizontal setup register constants.  All bits are r/w.  */
#define SFB_VID_HOR_BP_SHIFT	0x15		/* back porch */
#define SFB_VID_HOR_BP_MASK	0x7f
#define SFB_VID_HOR_SYN_SHIFT	0x0e		/* sync pulse */
#define SFB_VID_HOR_SYN_MASK	0x7f
#define SFB_VID_HOR_FP_SHIFT	0x09		/* front porch */
#define SFB_VID_HOR_FP_MASK	0x1f
#define SFB_VID_HOR_PIX_SHIFT	0x00		/* active video */
#define SFB_VID_HOR_PIX_MASK	0x1ff

/* Video vertical setup register constants.  All bits are r/w.  */
#define SFB_VID_VER_BP_SHIFT	0x16		/* back porch */
#define SFB_VID_VER_BP_MASK	0x3f
#define SFB_VID_VER_SYN_SHIFT	0x10		/* sync pulse */
#define SFB_VID_VER_SYN_MASK	0x3f
#define SFB_VID_VER_FP_SHIFT	0x0b		/* front porch */
#define SFB_VID_VER_FP_MASK	0x1f
#define SFB_VID_VER_SL_SHIFT	0x00		/* active scan lines */
#define SFB_VID_VER_SL_MASK	0x7ff

/* Video base address register constants.  All bits are r/w.  */
#define SFB_VID_BASE_MASK	0x1ff		/* video base row address */

/* Bt459 register offsets, byte-wide registers.  */
#define BT459_ADDR_LO		0x0		/* address low */
#define BT459_ADDR_HI		0x4		/* address high */
#define BT459_DATA		0x8		/* data window register */
#define BT459_CMAP		0xc		/* color map window register */
back to top