https://github.com/torvalds/linux
Revision bb6743f4f0aed5c1f09fa77cd8d3973c31792f4f authored by David S. Miller on 04 July 2005, 20:26:04 UTC, committed by David S. Miller on 04 July 2005, 20:26:04 UTC
This was the main impetus behind adding the PCI IRQ shim.

In order to properly order DMA writes wrt. interrupts, you have to
write to a PCI controller register, then poll for that bit clearing.
There is one bit for each interrupt source, and setting this register
bit tells Tomatillo to drain all pending DMA from that device.

Furthermore, Tomatillo's with revision less than 4 require us to do a
block store due to some memory transaction ordering issues it has on
JBUS.

Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent 088dd1f
History
Tip revision: bb6743f4f0aed5c1f09fa77cd8d3973c31792f4f authored by David S. Miller on 04 July 2005, 20:26:04 UTC
[SPARC64]: Do proper DMA IRQ syncing on Tomatillo
Tip revision: bb6743f

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