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Revision c6c292eed49f31f2f1c1d0ba295ae170fefd5a66 authored by Ron Burkey on 12 October 2018, 15:53:14 UTC, committed by Ron Burkey on 12 October 2018, 15:53:14 UTC 
Changed the yaYUL switches for building Validation-hardware-simulation,
 
to correspond to what's needed for conversion of the binary to Verilog.
1 parent 49926c6
History
File Mode Size
Artemis072
Aurora12
Borealis
Colossus237
Colossus249
Comanche055
Contributed
ControlPulseSim
FP6
FP8
GeminiCatchUpandRendezvousProgram
LMY99R0
LUM99R2
Luminary069
Luminary099
Luminary116
Luminary131
Luminary210
MessageBox
Pultorak-Simulator-1.16
Retread44
Solarium055
Sunburst120
Sunburst37
SuperJob
Tools
Validation
Validation-Block1
VirtualAGC
YUL
Zerlina56
agcSoftwareDocumentation
doc
enet
jWiz
piPeripheral
scenarios
scripts
sterm
yaACA
yaACA2
yaACA3
yaAGC
yaAGC-Block1-Pultorak
yaAGCb1
yaAGS
yaASM
yaDEDA
yaDEDA2
yaDSKY
yaDSKY2
yaDSKYb1
yaLEMAP
yaOBC
yaPanel
yaTelemetry
yaUniverse
yaUplinkBlock1
yaYUL
.DS_Store -rw-r--r-- 8.0 KB
.gitignore -rw-r--r-- 1.3 KB
.travis.yml -rw-r--r-- 127 bytes
AgcHtmlNotice.txt -rw-r--r-- 544 bytes
Apollo32.png -rw-r--r-- 2.6 KB
BuildBox.sh -rwxr-xr-x 1.2 KB
COPYING -rw-r--r-- 17.6 KB
Dockerfile -rw-r--r-- 346 bytes
Dockerfile.dev -rw-r--r-- 360 bytes
LICENSE.txt -rw-r--r-- 704 bytes
Makefile -rw-r--r-- 26.1 KB
Makefile.inc -rw-r--r-- 3.5 KB
Makefile.yaAGC -rw-r--r-- 18 bytes
README.md -rw-r--r-- 15.9 KB
TODO.txt -rw-r--r-- 216 bytes
configure -rwxr-xr-x 2.0 KB
nWayCompareAGC.sh -rwxr-xr-x 3.6 KB
templateAGC-bottom.cbp -rw-r--r-- 109 bytes
templateAGC-top.cbp -rw-r--r-- 994 bytes
transferListings.sh -rwxr-xr-x 1.1 KB

README.md

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