https://github.com/virtualagc/virtualagc
Revision c6c292eed49f31f2f1c1d0ba295ae170fefd5a66 authored by Ron Burkey on 12 October 2018, 15:53:14 UTC, committed by Ron Burkey on 12 October 2018, 15:53:14 UTC
to correspond to what's needed for conversion of the binary to Verilog.
1 parent 49926c6
History
Tip revision: c6c292eed49f31f2f1c1d0ba295ae170fefd5a66 authored by Ron Burkey on 12 October 2018, 15:53:14 UTC
Changed the yaYUL switches for building Validation-hardware-simulation,
Tip revision: c6c292e

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