https://github.com/torvalds/linux
Revision c760569d0e9c06b39dd19e82bff0b704d90a73b7 authored by Prathyush K on 10 July 2014, 23:02:15 UTC, committed by Kukjin Kim on 10 July 2014, 23:03:19 UTC
While powering on/off a local powerdomain in exynos5 chipsets, the
input clocks to each device gets modified. This behaviour is based
on the SYSCLK_SYS_PWR_REG registers.
E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC
(aclk333) gets modified to oscclk
= 0x1, no change in clocks.
The recommended value of SYSCLK_SYS_PWR_REG before power gating any
domain is 0x0. So we must also restore the clocks while powering on
a domain everytime.
This patch adds the framework for getting the required mux and parent
clocks through a power domain device node. With this patch, while
powering off a domain, parent is set to oscclk and while powering back
on, its re-set to the correct parent which is as per the recommended
pd on/off sequence.
Signed-off-by: Prathyush K <prathyush.k@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
1 parent be0b420
Tip revision: c760569d0e9c06b39dd19e82bff0b704d90a73b7 authored by Prathyush K on 10 July 2014, 23:02:15 UTC
ARM: EXYNOS: Add support for clock handling in power domain
ARM: EXYNOS: Add support for clock handling in power domain
Tip revision: c760569
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| crypto | ||
| drivers | ||
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| fs | ||
| include | ||
| init | ||
| ipc | ||
| kernel | ||
| lib | ||
| mm | ||
| net | ||
| samples | ||
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| security | ||
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| .gitignore | -rw-r--r-- | 1.1 KB |
| .mailmap | -rw-r--r-- | 4.4 KB |
| COPYING | -rw-r--r-- | 18.3 KB |
| CREDITS | -rw-r--r-- | 93.7 KB |
| Kbuild | -rw-r--r-- | 2.5 KB |
| Kconfig | -rw-r--r-- | 252 bytes |
| MAINTAINERS | -rw-r--r-- | 275.5 KB |
| Makefile | -rw-r--r-- | 51.0 KB |
| README | -rw-r--r-- | 18.3 KB |
| REPORTING-BUGS | -rw-r--r-- | 7.3 KB |
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