Revision c89cec3a4037f4aebf948d0f9c984c4823478c66 authored by Richard Genoud on 18 January 2013, 16:41:21 UTC, committed by Nicolas Ferre on 23 January 2013, 09:30:54 UTC
The PIN_BANK 3 is for PDxx pins, not PCxx pins. And PIN_BANK 1 is for PBxx, not PIN_BANK 0. Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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| File | Mode | Size |
|---|---|---|
| 00-INDEX | -rw-r--r-- | 458 bytes |
| MSI-HOWTO.txt | -rw-r--r-- | 15.3 KB |
| PCIEBUS-HOWTO.txt | -rw-r--r-- | 8.6 KB |
| pci-error-recovery.txt | -rw-r--r-- | 19.1 KB |
| pci-iov-howto.txt | -rw-r--r-- | 3.9 KB |
| pci.txt | -rw-r--r-- | 24.4 KB |
| pcieaer-howto.txt | -rw-r--r-- | 11.3 KB |
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