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13 August 2024, 17:29:01 UTC
Revision cccf34e9411c41b0cbfb41980fe55fc8e7c98fd2 authored by Markos Chandras on 10 July 2015, 08:29:10 UTC, committed by Ralf Baechle on 10 July 2015, 08:59:16 UTC 
MIPS: c-r4k: Fix cache flushing for MT cores
 
MT_SMP is not the only SMP option for MT cores. The MT_SMP option
allows more than one VPE per core to appear as a secondary CPU in the
system. Because of how CM works, it propagates the address-based
cache ops to the secondary cores but not the index-based ones.
Because of that, the code does not use IPIs to flush the L1 caches on
secondary cores because the CM would have done that already. However,
the CM functionality is independent of the type of SMP kernel so even in
non-MT kernels, IPIs are not necessary. As a result of which, we change
the conditional to depend on the CM presence. Moreover, since VPEs on
the same core share the same L1 caches, there is no need to send an
IPI on all of them so we calculate a suitable cpumask with only one
VPE per core.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10654/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1 parent 1c88535
History
Tip revision: cccf34e9411c41b0cbfb41980fe55fc8e7c98fd2 authored by Markos Chandras on 10 July 2015, 08:29:10 UTC
MIPS: c-r4k: Fix cache flushing for MT cores
Tip revision: cccf34e
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