https://github.com/torvalds/linux
Revision d2212b4dce596fee83e5c523400bf084f4cc816c authored by Will Deacon on 26 September 2013, 16:27:00 UTC, committed by Linus Torvalds on 27 September 2013, 16:15:01 UTC
The 64-bit cmpxchg operation on the lockref is ordered by virtue of
hazarding between the cmpxchg operation and the reference count
manipulation. On weakly ordered memory architectures (such as ARM), it
can be of great benefit to omit the barrier instructions where they are
not needed.

This patch moves the lockless lockref code over to a cmpxchg64_relaxed
operation, which doesn't provide barrier semantics. If the operation
isn't defined, we simply #define it as the usual 64-bit cmpxchg macro.

Cc: Waiman Long <Waiman.Long@hp.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
1 parent 4b97280
History
Tip revision: d2212b4dce596fee83e5c523400bf084f4cc816c authored by Will Deacon on 26 September 2013, 16:27:00 UTC
lockref: allow relaxed cmpxchg64 variant for lockless updates
Tip revision: d2212b4

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