swh:1:snp:c3bf2749e3476071fa748f67b0ffa2fdc5fe49d9
Revision d360a687d99577110c181e67ebfb9a1b6fed63a2 authored by Vladimir Murzin on 12 June 2017, 12:35:52 UTC, committed by Russell King on 12 June 2017, 14:47:29 UTC
Cache support is optional feature in M-class cores, thus DminLine or
IminLine of Cache Type Register is zero if caches are not implemented,
but we check the whole CTR which has other features encoded there.
Let's be more precise and check for DminLine and IminLine of CTR
before we set cacheid.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
1 parent bbeedfd
History
Tip revision: d1221cea11fca0f6946bdd032a45b22cecfc0f99 authored by Linus Torvalds on 13 September 2022, 13:11:38 UTC
Merge tag 'pull-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
Tip revision: d1221ce
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.cocciconfig -rw-r--r-- 59 bytes
.get_maintainer.ignore -rw-r--r-- 31 bytes
.gitattributes -rw-r--r-- 30 bytes
.gitignore -rw-r--r-- 1.3 KB
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