https://github.com/torvalds/linux
Revision d3cb8bf6081b8b7a2dabb1264fe968fd870fa595 authored by Mel Gorman on 02 October 2014, 18:47:41 UTC, committed by Linus Torvalds on 02 October 2014, 18:57:18 UTC
A migration entry is marked as write if pte_write was true at the time the
entry was created. The VMA protections are not double checked when migration
entries are being removed as mprotect marks write-migration-entries as
read. It means that potentially we take a spurious fault to mark PTEs write
again but it's straight-forward. However, there is a race between write
migrations being marked read and migrations finishing. This potentially
allows a PTE to be write that should have been read. Close this race by
double checking the VMA permissions using maybe_mkwrite when migration
completes.

[torvalds@linux-foundation.org: use maybe_mkwrite]
Cc: stable@vger.kernel.org
Signed-off-by: Mel Gorman <mgorman@suse.de>
Acked-by: Rik van Riel <riel@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
1 parent 50dddff
Raw File
Tip revision: d3cb8bf6081b8b7a2dabb1264fe968fd870fa595 authored by Mel Gorman on 02 October 2014, 18:47:41 UTC
mm: migrate: Close race between migration completion and mprotect
Tip revision: d3cb8bf
mic_overview.txt
An Intel MIC X100 device is a PCIe form factor add-in coprocessor
card based on the Intel Many Integrated Core (MIC) architecture
that runs a Linux OS. It is a PCIe endpoint in a platform and therefore
implements the three required standard address spaces i.e. configuration,
memory and I/O. The host OS loads a device driver as is typical for
PCIe devices. The card itself runs a bootstrap after reset that
transfers control to the card OS downloaded from the host driver. The
host driver supports OSPM suspend and resume operations. It shuts down
the card during suspend and reboots the card OS during resume.
The card OS as shipped by Intel is a Linux kernel with modifications
for the X100 devices.

Since it is a PCIe card, it does not have the ability to host hardware
devices for networking, storage and console. We provide these devices
on X100 coprocessors thus enabling a self-bootable equivalent environment
for applications. A key benefit of our solution is that it leverages
the standard virtio framework for network, disk and console devices,
though in our case the virtio framework is used across a PCIe bus.

MIC PCIe card has a dma controller with 8 channels. These channels are
shared between the host s/w and the card s/w. 0 to 3 are used by host
and 4 to 7 by card. As the dma device doesn't show up as PCIe device,
a virtual bus called mic bus is created and virtual dma devices are
created on it by the host/card drivers. On host the channels are private
and used only by the host driver to transfer data for the virtio devices.

Here is a block diagram of the various components described above. The
virtio backends are situated on the host rather than the card given better
single threaded performance for the host compared to MIC, the ability of
the host to initiate DMA's to/from the card using the MIC DMA engine and
the fact that the virtio block storage backend can only be on the host.

                                      |
               +----------+           |             +----------+
               | Card OS  |           |             | Host OS  |
               +----------+           |             +----------+
                                      |
        +-------+ +--------+ +------+ | +---------+  +--------+ +--------+
        | Virtio| |Virtio  | |Virtio| | |Virtio   |  |Virtio  | |Virtio  |
        | Net   | |Console | |Block | | |Net      |  |Console | |Block   |
        | Driver| |Driver  | |Driver| | |backend  |  |backend | |backend |
        +-------+ +--------+ +------+ | +---------+  +--------+ +--------+
            |         |         |     |      |            |         |
            |         |         |     |User  |            |         |
            |         |         |     |------|------------|---------|-------
            +-------------------+     |Kernel +--------------------------+
                      |               |       | Virtio over PCIe IOCTLs  |
                      |               |       +--------------------------+
+-----------+         |               |                   |  +-----------+
| MIC DMA   |         |               |                   |  | MIC DMA   |
| Driver    |         |               |                   |  | Driver    |
+-----------+         |               |                   |  +-----------+
      |               |               |                   |        |
+---------------+     |               |                   |  +----------------+
|MIC virtual Bus|     |               |                   |  |MIC virtual Bus |
+---------------+     |               |                   |  +----------------+
      |               |               |                   |              |
      |   +--------------+            |            +---------------+     |
      |   |Intel MIC     |            |            |Intel MIC      |     |
      +---|Card Driver   |            |            |Host Driver    |     |
          +--------------+            |            +---------------+-----+
                      |               |                   |
             +-------------------------------------------------------------+
             |                                                             |
             |                    PCIe Bus                                 |
             +-------------------------------------------------------------+
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