Revision d411cf02ed0260dacc4b2fd61dd5040fc2aa97e7 authored by Greentime Hu on 19 December 2019, 06:44:59 UTC, committed by Paul Walmsley on 20 December 2019, 11:32:24 UTC
This patch fixes that the sscratch register clearing in M-mode. It cleared
sscratch register in M-mode, but it should clear mscratch register. That will
cause kernel trap if the CPU core doesn't support S-mode when trying to access
sscratch.
Fixes: 9e80635619b5 ("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> 1 parent 0312a3d
| File | Mode | Size |
|---|---|---|
| Makefile | -rw-r--r-- | 418 bytes |
| generic_mpih-add1.c | -rw-r--r-- | 1.3 KB |
| generic_mpih-lshift.c | -rw-r--r-- | 1.5 KB |
| generic_mpih-mul1.c | -rw-r--r-- | 1.3 KB |
| generic_mpih-mul2.c | -rw-r--r-- | 1.3 KB |
| generic_mpih-mul3.c | -rw-r--r-- | 1.3 KB |
| generic_mpih-rshift.c | -rw-r--r-- | 1.5 KB |
| generic_mpih-sub1.c | -rw-r--r-- | 1.3 KB |
| longlong.h | -rw-r--r-- | 39.0 KB |
| mpi-bit.c | -rw-r--r-- | 1.5 KB |
| mpi-cmp.c | -rw-r--r-- | 1.6 KB |
| mpi-inline.h | -rw-r--r-- | 2.6 KB |
| mpi-internal.h | -rw-r--r-- | 5.3 KB |
| mpi-pow.c | -rw-r--r-- | 7.7 KB |
| mpicoder.c | -rw-r--r-- | 9.0 KB |
| mpih-cmp.c | -rw-r--r-- | 1.3 KB |
| mpih-div.c | -rw-r--r-- | 5.2 KB |
| mpih-mul.c | -rw-r--r-- | 13.6 KB |
| mpiutil.c | -rw-r--r-- | 2.7 KB |
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