Revision d6ee1e7e9004d3d246cdfa14196989e0a9466c16 authored by Jerome Brunet on 08 November 2018, 09:31:23 UTC, committed by Stephen Boyd on 08 November 2018, 18:21:21 UTC
Similar to gxbb and gxl platforms, axg SCPI Cortex-M co-processor uses the fdiv2 and fdiv3 to, among other things, provide the cpu clock. Until clock hand-off mechanism makes its way to CCF and the generic SCPI claims platform specific clocks, these clocks must be marked as critical to make sure they are never disabled when needed by the co-processor. Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
1 parent e2576c8
dump_linuxpagetables-book3s64.c
// SPDX-License-Identifier: GPL-2.0
/*
* From split of dump_linuxpagetables.c
* Copyright 2016, Rashmica Gupta, IBM Corp.
*
*/
#include <linux/kernel.h>
#include <asm/pgtable.h>
#include "dump_linuxpagetables.h"
static const struct flag_info flag_array[] = {
{
.mask = _PAGE_PRIVILEGED,
.val = 0,
.set = "user",
.clear = " ",
}, {
.mask = _PAGE_READ,
.val = _PAGE_READ,
.set = "r",
.clear = " ",
}, {
.mask = _PAGE_WRITE,
.val = _PAGE_WRITE,
.set = "w",
.clear = " ",
}, {
.mask = _PAGE_EXEC,
.val = _PAGE_EXEC,
.set = " X ",
.clear = " ",
}, {
.mask = _PAGE_PTE,
.val = _PAGE_PTE,
.set = "pte",
.clear = " ",
}, {
.mask = _PAGE_PRESENT,
.val = _PAGE_PRESENT,
.set = "valid",
.clear = " ",
}, {
.mask = _PAGE_PRESENT | _PAGE_INVALID,
.val = 0,
.set = " ",
.clear = "present",
}, {
.mask = H_PAGE_HASHPTE,
.val = H_PAGE_HASHPTE,
.set = "hpte",
.clear = " ",
}, {
.mask = _PAGE_DIRTY,
.val = _PAGE_DIRTY,
.set = "dirty",
.clear = " ",
}, {
.mask = _PAGE_ACCESSED,
.val = _PAGE_ACCESSED,
.set = "accessed",
.clear = " ",
}, {
.mask = _PAGE_NON_IDEMPOTENT,
.val = _PAGE_NON_IDEMPOTENT,
.set = "non-idempotent",
.clear = " ",
}, {
.mask = _PAGE_TOLERANT,
.val = _PAGE_TOLERANT,
.set = "tolerant",
.clear = " ",
}, {
.mask = H_PAGE_BUSY,
.val = H_PAGE_BUSY,
.set = "busy",
}, {
#ifdef CONFIG_PPC_64K_PAGES
.mask = H_PAGE_COMBO,
.val = H_PAGE_COMBO,
.set = "combo",
}, {
.mask = H_PAGE_4K_PFN,
.val = H_PAGE_4K_PFN,
.set = "4K_pfn",
}, {
#else /* CONFIG_PPC_64K_PAGES */
.mask = H_PAGE_F_GIX,
.val = H_PAGE_F_GIX,
.set = "f_gix",
.is_val = true,
.shift = H_PAGE_F_GIX_SHIFT,
}, {
.mask = H_PAGE_F_SECOND,
.val = H_PAGE_F_SECOND,
.set = "f_second",
}, {
#endif /* CONFIG_PPC_64K_PAGES */
.mask = _PAGE_SPECIAL,
.val = _PAGE_SPECIAL,
.set = "special",
}
};
struct pgtable_level pg_level[5] = {
{
}, { /* pgd */
.flag = flag_array,
.num = ARRAY_SIZE(flag_array),
}, { /* pud */
.flag = flag_array,
.num = ARRAY_SIZE(flag_array),
}, { /* pmd */
.flag = flag_array,
.num = ARRAY_SIZE(flag_array),
}, { /* pte */
.flag = flag_array,
.num = ARRAY_SIZE(flag_array),
},
};
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