Revision d8579dde956f095d9dc53d45dcf4b78cd6234751 authored by Matt Anderson on 19 June 2019, 08:01:37 UTC, committed by Karl Palsson on 17 October 2019, 21:26:13 UTC
For ARMv6M, the IPR and SHPR registers are accessible only when adddressed with a 32bit word read or write. Currently in libopencm3 all NVIC interrupt priority register accesses are made using an 8bit read or write, which results in the hardware ignoring the write or always returning 0 on read. Address this by introducing NVIC_IPR32() and SCS_SHPR32() macro and conditional implementation of nvic_set_priority when building for cortex-m0. See ARMv6M developer documentation: IPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/Cihgjeed.html SHPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CIAGECDD.html
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| .gitignore | -rw-r--r-- | 822 bytes |
| .travis.yml | -rw-r--r-- | 272 bytes |
| COPYING.GPL3 | -rw-r--r-- | 34.2 KB |
| COPYING.LGPL3 | -rw-r--r-- | 7.5 KB |
| HACKING | -rw-r--r-- | 3.4 KB |
| HACKING_COMMON_DOC | -rw-r--r-- | 3.0 KB |
| Makefile | -rw-r--r-- | 3.7 KB |
| README.md | -rw-r--r-- | 6.7 KB |
| locm3.sublime-project | -rw-r--r-- | 486 bytes |
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