https://github.com/torvalds/linux
Revision da30e0ac0f9a521f0cfec8145ddd1ad131f66d61 authored by Catalin Marinas on 07 December 2010, 15:56:29 UTC, committed by Russell King on 12 December 2010, 23:25:58 UTC
The current implementation of the v7_coherent_*_range function assumes
that the D and I cache lines have the same size, which is incorrect
architecturally. This patch adds the icache_line_size macro which reads
the CTR register. The main loop in v7_coherent_*_range is split in two
independent loops or the D and I caches. This also has the performance
advantage that the DSB is moved outside the main loop.

Reported-by: Kevin Sapp <ksapp@quicinc.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1 parent f91e2c3
History
Tip revision: da30e0ac0f9a521f0cfec8145ddd1ad131f66d61 authored by Catalin Marinas on 07 December 2010, 15:56:29 UTC
ARM: 6528/1: Use CTR for the I-cache line size on ARMv7
Tip revision: da30e0a
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