https://github.com/torvalds/linux
Revision dc6fcba72f0435b7884f2e92fd634bb9f78a2c60 authored by Guo Ren on 05 January 2020, 02:52:14 UTC, committed by Paul Walmsley on 12 January 2020, 18:12:44 UTC
CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
ISA Register misa. Every bit:1 indicate a feature, so we should beqz
reset_done when there is no F/D bit in csr_misa register.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
[paul.walmsley@sifive.com: fix typo in commit message]
Fixes: 9e80635619b51 ("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
1 parent 13cf4cf
History
Tip revision: dc6fcba72f0435b7884f2e92fd634bb9f78a2c60 authored by Guo Ren on 05 January 2020, 02:52:14 UTC
riscv: Fixup obvious bug for fp-regs reset
Tip revision: dc6fcba
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