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swh:1:snp:3c665ee4f67729f27f2e40193ab88e7298cf0fef
Revision e06a1548f3043febb658b58ec5ccbc7d03a785af authored by James Hogan on 11 May 2016, 12:50:51 UTC, committed by Ralf Baechle on 13 May 2016, 13:30:25 UTC 
MIPS: Add defs & probing of BadInstr[P] registers
 
The optional CP0_BadInstr and CP0_BadInstrP registers are written with
the encoding of the instruction that caused a synchronous exception to
occur, and the prior branch instruction if in a delay slot.

These will be useful for instruction emulation in KVM, and especially
for VZ support where reading guest virtual memory is a bit more awkward.

Add CPU option numbers and cpu_has_* definitions to indicate the
presence of each registers, and add code to probe for them using bits in
the CP0_Config3 register.

[ralf@linux-mips.org: resolve merge conflict.]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13224/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1 parent 37fb60f
History
Tip revision: 64222515138e43da1fcf288f0289ef1020427b87 authored by Linus Torvalds on 22 October 2021, 05:06:08 UTC
Merge tag 'drm-fixes-2021-10-22' of git://anongit.freedesktop.org/drm/drm
Tip revision: 6422251
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