| e7d7705 | Bjorn Helgaas | 12 October 2016, 03:06:47 UTC | PCI: imx6: Pass device-specific struct to internal functions Only interfaces used from outside the driver, e.g., those called by the DesignWare core, need to accept pointers to the generic struct pcie_port. Internal interfaces can accept pointers to the device-specific struct, which makes them more straightforward. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 12 October 2016, 03:26:28 UTC |
| 8bad7f2 | Bjorn Helgaas | 12 October 2016, 03:09:32 UTC | PCI: imx6: Pass struct imx6_pcie to PHY accessors Pass the struct imx6_pcie pointer, not dbi_base address, to PHY accessors. This enables future simplifications. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 12 October 2016, 03:09:32 UTC |
| 51c8470 | Bjorn Helgaas | 06 October 2016, 18:35:17 UTC | PCI: imx6: Removed unused struct imx6_pcie.mem_base Removed the unused struct imx6_pcie.mem_base member. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 12 October 2016, 03:03:40 UTC |
| c5af407 | Bjorn Helgaas | 06 October 2016, 18:35:18 UTC | PCI: imx6: Remove redundant of_node pointer "np" and "node" are redundant copies of the of_node pointer. Remove "np" and use "node" instead. Replace the "fsl,max-link-speed" use with "node" as well. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 12 October 2016, 03:00:50 UTC |
| 1395765 | Bjorn Helgaas | 06 October 2016, 18:35:18 UTC | PCI: imx6: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 12 October 2016, 02:54:51 UTC |
| f5acb5c | Bjorn Helgaas | 11 October 2016, 13:33:00 UTC | PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val arguments Swap order of dw_pcie_readl_unroll() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 11 October 2016, 13:34:47 UTC |
| 3d46993 | Bjorn Helgaas | 11 October 2016, 13:33:33 UTC | PCI: designware: Uninline register accessors The register accessors are not performance critical and small enough that the compiler can inline them itself if it makes sense. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 11 October 2016, 13:33:58 UTC |
| 8ad7501 | Bjorn Helgaas | 06 October 2016, 18:25:47 UTC | PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc() Export dw_pcie_readl_rc() and dw_pcie_writel_rc(). Many other drivers can use these instead of implementing their own versions. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 11 October 2016, 13:31:52 UTC |
| ad88021 | Bjorn Helgaas | 06 October 2016, 18:25:46 UTC | PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 11 October 2016, 13:30:33 UTC |
| 7e00dfd | Bjorn Helgaas | 06 October 2016, 18:25:46 UTC | PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers allow a driver to override the default DesignWare register accessors. Make the signature of the override functions the same as the default accessors. This makes the default dw_pcie_readl_rc() and the corresponding override more structurally similar: both will compute the final register address with "pp->dbi_base + reg". Previously dw_pcie_readl_rc() computed the address and passed it to the override. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 11 October 2016, 13:29:25 UTC |
| a26e010 | Kishon Vijay Abraham I | 11 October 2016, 13:26:21 UTC | PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll() dw_pcie_readl_unroll() and dw_pcie_writel_unroll() duplicate what dw_pcie_readl_rc() and dw_pcie_writel_rc() already do, so call them directly. [bhelgaas: reworked into patch series] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 11 October 2016, 13:26:21 UTC |
| 1034023 | Bjorn Helgaas | 06 October 2016, 18:25:46 UTC | PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device() Rename dw_pcie_valid_config() to dw_pcie_valid_device() and use the result directly as a boolean value instead of testing against 0. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 06 October 2016, 18:25:46 UTC |
| bdf5309 | Bjorn Helgaas | 05 October 2016, 19:00:21 UTC | Merge branch 'pci/host-vmd' into next * pci/host-vmd: x86/PCI: VMD: Move VMD driver to drivers/pci/host x86/PCI: VMD: Synchronize with RCU freeing MSI IRQ descs x86/PCI: VMD: Eliminate index member from IRQ list x86/PCI: VMD: Eliminate vmd_vector member from list type x86/PCI: VMD: Convert to use pci_alloc_irq_vectors() API x86/PCI: VMD: Allocate IRQ lists with correct MSI-X count PCI: Use positive flags in pci_alloc_irq_vectors() PCI: Update "pci=resource_alignment" documentation Conflicts: drivers/pci/host/Kconfig drivers/pci/host/Makefile | 05 October 2016, 19:00:21 UTC |
| 69a06e4 | Bjorn Helgaas | 05 October 2016, 18:59:14 UTC | Merge branches 'pci/host-aardvark', 'pci/host-altera', 'pci/host-artpec', 'pci/host-designware', 'pci/host-hv', 'pci/host-keystone', 'pci/host-rcar', 'pci/host-rockchip', 'pci/host-tegra' and 'pci/host-xilinx' into next * pci/host-aardvark: PCI: aardvark: Remove redundant dev_err call in advk_pcie_probe() * pci/host-altera: PCI: altera: Remove redundant platform_get_resource() return value check PCI: altera: Move retrain from fixup to altera_pcie_host_init() PCI: altera: Rework config accessors for use without a struct pci_bus PCI: altera: Poll for link training status after retraining the link * pci/host-artpec: PCI: artpec6: Drop __init from artpec6_add_pcie_port() * pci/host-designware: PCI: designware: Remove redundant platform_get_resource() return value check PCI: designware: Exchange viewport of `MEMORYs' and `CFGs/IOs' PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2 PCI: designware: Check LTSSM training bit before deciding link is up PCI: designware: Add iATU Unroll feature PCI: designware: Wait for iATU enable PCI: designware: Move link wait definitions to .c file PCI: designware: Return data directly from dw_pcie_readl_rc() * pci/host-hv: PCI: hv: Handle hv_pci_generic_compl() error case PCI: hv: Handle vmbus_sendpacket() failure in hv_compose_msi_msg() PCI: hv: Remove the unused 'wrk' in struct hv_pcibus_device PCI: hv: Use pci_function_description[0] in struct definitions PCI: hv: Use zero-length array in struct pci_packet PCI: hv: Use list_move_tail() instead of list_del() + list_add_tail() * pci/host-keystone: PCI: keystone: Propagate request_irq() failure * pci/host-rcar: PCI: rcar: Try increasing PCIe link speed to 5 GT/s at boot PCI: rcar: Fix some checkpatch warnings PCI: rcar: Add multi-MSI support PCI: rcar: Don't disable/unprepare clocks on prepare/enable failure PCI: rcar: Consolidate register space lookup and ioremap * pci/host-rockchip: PCI: rockchip: Fix wrong transmitted FTS count PCI: rockchip: Improve the deassert sequence of four reset pins PCI: rockchip: Increase the Max Credit update interval PCI: rockchip: Add Rockchip PCIe controller support dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe controller * pci/host-tegra: PCI: tegra: Use of_device_get_match_data() PCI: tegra: Remove redundant _data suffix * pci/host-xilinx: microblaze/PCI: Add multidomain support for procfs PCI: xilinx: Dispose of MSI virtual IRQ PCI: xilinx: Clear correct MSI set bit PCI: xilinx: Clear interrupt register for invalid interrupt PCI: xilinx: Keep both legacy and MSI interrupt domain references PCI: xilinx-nwl: Enable all MSI interrupts using MSI mask PCI: xilinx-nwl: Expand error logging Conflicts: drivers/pci/host/pcie-xilinx.c | 05 October 2016, 18:59:14 UTC |
| 181ffd1 | Keith Busch | 04 October 2016, 17:26:37 UTC | x86/PCI: VMD: Move VMD driver to drivers/pci/host Move the driver source and Kconfig to the PCI host bridge drivers directory and move the config option to a more appropriate sub-menu instead of occupying the top-level location. Update the Kconfig option with the X86_64 dependency that was implicitly included from the previous location, and add information about the module name when built as a loadable module. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jon Derrick <jonathan.derrick@intel.com> | 04 October 2016, 17:26:37 UTC |
| ca19890 | Shawn Lin | 04 October 2016, 17:20:22 UTC | PCI: rockchip: Fix wrong transmitted FTS count If the expected number of FTS aren't received by RC when exiting from L0s, the LTSSM will fall into recover state, which means it will need to send TS for retraining which makes the latency of exiting from L0s a little longer than expected. This issue is caused by an incorrect reset value of FTS count on PLC1 register (offset 0x4). The expected value for Gen1/2 should be more than 240 and we may leave a little margin here. Fix this before starting Gen1 training which will make TS1 contain the correct FTS count. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 04 October 2016, 17:20:22 UTC |
| 58c6990 | Shawn Lin | 23 September 2016, 02:05:59 UTC | PCI: rockchip: Improve the deassert sequence of four reset pins Per TRM, we need to deassert the four reset pins simultaneously. Currently the reset framework doesn't support that so we did it one by one. It seems no side effect found but it does impact the state machine of controller, so sometimes the change speed bit is not set when sending training sequence from recover state. After the silicon RTL review from SoC guys, we don't need to do the sequence recommended by TRM, and could just move the deassert of mgmt_sticky_rst to the first place. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 04 October 2016, 17:18:25 UTC |
| 277743e | Rajat Jain | 23 September 2016, 00:50:42 UTC | PCI: rockchip: Increase the Max Credit update interval Increase the likelihood of link state to automatically go to L1 and save some power. The default credit update interval of 7.5 us results in the rootport sending UpdateFC-P and UpdateFC-NP packets too often, thus resulting in the link never going to L1, and always staying in L0/L0s. The value 24 us was chosen after some experiments and peeking over the PCIe bus to see that we do enter L1 substate when there is not enough traffic on the PCIe bus. Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com> | 04 October 2016, 17:16:03 UTC |
| b3327f7 | Sergei Shtylyov | 22 September 2016, 20:20:18 UTC | PCI: rcar: Try increasing PCIe link speed to 5 GT/s at boot The PCIe link speed is initially set to 2.5 GT/s. Try to increase the link speed to 5 GT/s. Based on original patch by Grigory Kletsko <grigory.kletsko@cogentembedded.com>. [bhelgaas: remove "Trying speed up" message, remove unused SPCHG] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> | 04 October 2016, 16:42:39 UTC |
| 930ffc0 | Bjorn Helgaas | 03 October 2016, 14:43:21 UTC | Merge branch 'pci/virtualization' into next * pci/virtualization: PCI: xilinx: Relax device number checking to allow SR-IOV PCI: designware: Relax device number checking to allow SR-IOV PCI: altera: Relax device number checking to allow SR-IOV PCI: Check for pci_setup_device() failure in pci_iov_add_virtfn() PCI: Mark Atheros AR9580 to avoid bus reset | 03 October 2016, 14:43:21 UTC |
| e15194d | Bjorn Helgaas | 03 October 2016, 14:43:21 UTC | Merge branch 'pci/resource' into next * pci/resource: PCI: Ignore requested alignment for VF BARs PCI: Ignore requested alignment for PROBE_ONLY and fixed resources | 03 October 2016, 14:43:21 UTC |
| 3f4f356 | Bjorn Helgaas | 03 October 2016, 14:43:21 UTC | Merge branch 'pci/pm' into next * pci/pm: PCI: Avoid unnecessary resume after direct-complete PCI: Recognize D3cold in pci_update_current_state() PCI: Query platform firmware for device power state PCI: Afford direct-complete to devices with non-standard PM | 03 October 2016, 14:43:21 UTC |
| 6c6cba4 | Bjorn Helgaas | 03 October 2016, 14:43:20 UTC | Merge branch 'pci/msi' into next * pci/msi: PCI/MSI: Enable PCI_MSI_IRQ_DOMAIN support for ARC | 03 October 2016, 14:43:20 UTC |
| 5485e49 | Bjorn Helgaas | 03 October 2016, 14:43:20 UTC | Merge branch 'pci/misc' into next * pci/misc: PCI: Drop CONFIG_KEXEC_CORE ifdeffery | 03 October 2016, 14:43:20 UTC |
| 64ea3b9 | Bjorn Helgaas | 03 October 2016, 14:43:19 UTC | Merge branch 'pci/hotplug' into next * pci/hotplug: x86/PCI: VMD: Request userspace control of PCIe hotplug indicators PCI: pciehp: Allow exclusive userspace control of indicators PCI: pciehp: Remove useless pciehp_get_latch_status() calls PCI: pciehp: Clean up dmesg "Slot(%s)" messages PCI: pciehp: Remove unnecessary guard PCI: pciehp: Don't re-read Slot Status when handling surprise event PCI: pciehp: Don't re-read Slot Status when queuing hotplug event PCI: pciehp: Process all hotplug events before looking for new ones PCI: pciehp: Return IRQ_NONE when we can't read interrupt status PCI: pciehp: Rename pcie_isr() locals for clarity PCI: pciehp: Clear attention LED on device add | 03 October 2016, 14:43:19 UTC |
| fb6b6cc | Bjorn Helgaas | 03 October 2016, 14:43:19 UTC | Merge branch 'pci/enumeration' into next * pci/enumeration: PCI: tegra: Fix pci_remap_iospace() failure path PCI: generic: Fix pci_remap_iospace() failure path PCI: rcar: Fix pci_remap_iospace() failure path PCI: versatile: Fix pci_remap_iospace() failure path PCI: designware: Fix pci_remap_iospace() failure path PCI: aardvark: Fix pci_remap_iospace() failure path | 03 October 2016, 14:43:19 UTC |
| 4dc2db0 | Bjorn Helgaas | 03 October 2016, 14:42:57 UTC | Merge branch 'pci/aer' into next * pci/aer: PCI/AER: Fix aer_probe() kernel-doc comment PCI/AER: Cache capability position PCI/AER: Avoid memory allocation in interrupt handling path ACPI / APEI: Send correct severity to calculate AER severity PCI/AER: Remove duplicate AER severity translation PCI/AER: Remove aerdriver.forceload kernel parameter PCI/AER: Remove aerdriver.nosourceid kernel parameter x86/PCI: VMD: Add quirk for AER to ignore source ID PCI/AER: Add bus flag to skip source ID matching Conflicts: drivers/pci/probe.c | 03 October 2016, 14:42:57 UTC |
| 6b20f72 | Cao jin | 30 September 2016, 15:06:23 UTC | PCI/AER: Fix aer_probe() kernel-doc comment 0516c8bcd252 ("PCI: PCIe portdrv: Simplily probe callback of service drivers") removed the "id" argument of aer_probe() but neglected to remove the kernel-doc comment. Update the comment. [bhelgaas: changelog] Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 30 September 2016, 15:06:23 UTC |
| 62d9a78 | Yongji Xie | 13 September 2016, 09:00:32 UTC | PCI: Ignore requested alignment for VF BARs Resource allocation for VFs is done via the VF BARx registers in the PF's SR-IOV Capability, and the BARs in the VFs themselves are read-only zeros (see SR-IOV spec r1.1, secs 3.3.14 and 3.4.1.11). Even though the actual VF BARs are read-only zeros, the VF dev->resource[] structs describe the space allocated for the VF (this is a piece of the space described by the VF BARx register in the PF's SR-IOV capability). It's meaningless to request additional alignment for a VF: the VF BAR alignment is completely determined by the alignment of the VF BARx in the PF and the size of the VF BAR. Ignore the user's alignment requests for VF devices. Signed-off-by: Yongji Xie <xyjxie@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 28 September 2016, 22:17:20 UTC |
| f0b99f7 | Yongji Xie | 13 September 2016, 09:00:31 UTC | PCI: Ignore requested alignment for PROBE_ONLY and fixed resources Users may request additional alignment of PCI resources, e.g., to align BARs on page boundaries so they can be shared with guests via VFIO. This of course may require reallocation if firmware has already assigned the BARs with smaller alignments. If the platform has requested PCI_PROBE_ONLY, we should never change any PCI BARs, so we can't provide any additional alignment. Also, if a BAR is marked as IORESOURCE_PCI_FIXED, e.g., for PCI Enhanced Allocation or if the firmware depends on the current BAR value, we can't change the alignment. In these cases, log a message and ignore the user's alignment requests. [bhelgaas: changelog, use goto to simplify PCI_PROBE_ONLY check] Signed-off-by: Yongji Xie <xyjxie@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 28 September 2016, 21:44:52 UTC |
| a0d2a95 | Lukas Wunner | 18 September 2016, 03:39:20 UTC | PCI: Avoid unnecessary resume after direct-complete Commit 58a1fbbb2ee8 ("PM / PCI / ACPI: Kick devices that might have been reset by firmware") added a runtime resume for devices that were runtime suspended when the system entered sleep. The motivation was that devices might be in a reset-power-on state after waking from system sleep, so their power state as perceived by Linux (stored in pci_dev->current_state) would no longer reflect reality. By resuming such devices, we allow them to return to a low-power state via autosuspend and also bring their current_state in sync with reality. However for devices that are *not* in a reset-power-on state, doing an unconditional resume wastes energy. A more refined approach is called for which issues a runtime resume only if the power state after direct-complete is shallower than it was before. To achieve this, update the device's current_state and compare it to its pre-sleep value. Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 28 September 2016, 16:49:21 UTC |
| a6a6402 | Lukas Wunner | 18 September 2016, 03:39:20 UTC | PCI: Recognize D3cold in pci_update_current_state() Whenever a device is resumed or its power state is changed using the platform, its new power state is read from the PM Control & Status Register and cached in pci_dev->current_state by calling pci_update_current_state(). If the device is in D3cold, reading from config space typically results in a fabricated "all ones" response. But if it's in D3hot, the two bits representing the power state in the PMCSR are *also* set to 1. Thus D3hot and D3cold are not discernible by just reading the PMCSR. To account for this, pci_update_current_state() uses two workarounds: - When transitioning to D3cold using pci_platform_power_transition(), the new power state is set blindly by pci_update_current_state(), i.e. without verifying that the device actually *is* in D3cold. This is achieved by setting the "state" argument to PCI_D3cold. The "state" argument was originally intended to convey the new state in case the device doesn't have the PM capability. It is *also* used to convey the device state if the PM capability is present and the new state is D3cold, but this was never explained in the kerneldoc. - Once the current_state is set to D3cold, further invocations of pci_update_current_state() will blindly assume that the device is still in D3cold and leave the current_state unmodified. To get out of this impasse, the current_state has to be set directly, typically by calling pci_raw_set_power_state() or pci_enable_device(). It would be desirable if pci_update_current_state() could reliably detect D3cold by itself. That would allow us to do away with these workarounds, and it would allow for a smarter, more energy conserving runtime resume strategy after system sleep: Currently devices which utilize direct_complete are mandatorily runtime resumed in their ->complete stage. This can be avoided if their power state after system sleep is the same as before, but it requires a mechanism to detect the power state reliably. We've just gained the ability to query the platform firmware for its opinion on the device's power state. On platforms conforming to ACPI 4.0 or newer, this allows recognition of D3cold. Pre-4.0 platforms lack _PR3 and therefore the deepest power state that will ever be reported is D3hot, even though the device may actually be in D3cold. To detect D3cold in those cases, accessibility of the vendor ID in config space is probed using pci_device_is_present(). This also works for devices which are not platform-power-manageable at all, but can be suspended to D3cold using a nonstandard mechanism (e.g. some hybrid graphics laptops or Thunderbolt on the Mac). Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 28 September 2016, 16:47:38 UTC |
| cc7cc02 | Lukas Wunner | 18 September 2016, 03:39:20 UTC | PCI: Query platform firmware for device power state Usually the most accurate way to determine a PCI device's power state is to read its PM Control & Status Register. There are two cases however when this is not an option: If the device doesn't have the PM capability at all, or if it is in D3cold (in which case its config space is inaccessible). In both cases, we can alternatively query the platform firmware for its opinion on the device's power state. To facilitate this, augment struct pci_platform_pm_ops with a ->get_power callback and implement it for acpi_pci_platform_pm (the only pci_platform_pm_ops existing so far). It is used by a forthcoming commit to let pci_update_current_state() recognize D3cold. Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 28 September 2016, 16:46:51 UTC |
| 4132a57 | Lukas Wunner | 18 September 2016, 03:39:20 UTC | PCI: Afford direct-complete to devices with non-standard PM There are devices not power-manageable by the platform, but still able to runtime suspend to D3cold with a non-standard mechanism. One example is laptop hybrid graphics where the discrete GPU and its built-in HDA controller are power-managed either with a _DSM (AMD PowerXpress, Nvidia Optimus) or a separate gmux controller (MacBook Pro). Another example is Thunderbolt on Macs which is power-managed with custom ACPI methods. When putting the system to sleep, we currently handle such devices improperly by transitioning them from D3cold to D3hot (the default power state defined at the top of pci_target_state()). This wastes energy and prolongs the suspend sequence (powering up the Thunderbolt controller takes 2 seconds). Avoid that by assuming that a non-standard PM mechanism is at work if the device is not platform-power-manageable but currently in D3cold. If the device is wakeup enabled, we might still have to wake it up from D3cold if PME cannot be signaled from that power state. The check for devices without PM capability comes before the check for D3cold since such devices could in theory also be powered down by non-standard means and should then be afforded direct-complete as well. Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 28 September 2016, 16:45:27 UTC |
| 66b8080 | Keith Busch | 27 September 2016, 20:23:34 UTC | PCI/AER: Cache capability position Save the position of the error reporting capability so it doesn't need to be rediscovered during error handling. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Lukas Wunner <lukas@wunner.de> | 27 September 2016, 21:01:49 UTC |
| 4b202b7 | Jon Derrick | 14 September 2016, 16:38:55 UTC | PCI/AER: Avoid memory allocation in interrupt handling path When handling AER events, we previously allocated a struct aer_err_info, processed the error, and freed the struct. But aer_isr_one_error() is serialized by rpc_mutex, so we never need more than one copy of the struct, and the struct is only about 70 bytes, so we're not saving much by allocating it dynamically. Embed a struct aer_err_info directly in struct aer_rpc, which is allocated at probe-time by aer_probe(). [bhelgaas: changelog] Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 27 September 2016, 19:30:36 UTC |
| 3161832 | Keith Busch | 13 September 2016, 15:05:40 UTC | x86/PCI: VMD: Request userspace control of PCIe hotplug indicators Add set_dev_domain_options() to set PCI domain-specific options as devices are added. The first usage is to request exclusive userspace control of PCIe hotplug indicators in VMD domains. Devices in a VMD domain use PCIe hotplug Attention and Power Indicators in a non-standard way; tell pciehp to ignore the indicators so userspace can control them via the sysfs "attention" file. To determine whether a bus is within a VMD domain, add a bool to the pci_sysdata structure that the VMD driver sets during initialization. [bhelgaas: changelog] Requested-by: Kapil Karkra <kapil.karkra@intel.com> Tested-by: Artur Paszkiewicz <artur.paszkiewicz@intel.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 23 September 2016, 13:41:08 UTC |
| 576243b | Keith Busch | 13 September 2016, 16:31:59 UTC | PCI: pciehp: Allow exclusive userspace control of indicators PCIe hotplug supports optional Attention and Power Indicators, which are used internally by pciehp. Users can't control the Power Indicator, but they can control the Attention Indicator by writing to a sysfs "attention" file. The Slot Control register has two bits for each indicator, and the PCIe spec defines the encodings for each as (Reserved/On/Blinking/Off). For sysfs "attention" writes, pciehp_set_attention_status() maps into these encodings, so the only useful write values are 0 (Off), 1 (On), and 2 (Blinking). However, some platforms use all four bits for platform-specific indicators, and they need to allow direct user control of them while preventing pciehp from using them at all. Add a "hotplug_user_indicators" flag to the pci_dev structure. When set, pciehp does not use either the Attention Indicator or the Power Indicator, and the low four bits (values 0x0 - 0xf) of sysfs "attention" write values are written directly to the Attention Indicator Control and Power Indicator Control fields. [bhelgaas: changelog, rename flag and accessors to s/attention/indicator/] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 22 September 2016, 23:20:11 UTC |
| 2458d66 | Tyler Baicar | 14 September 2016, 21:14:46 UTC | ACPI / APEI: Send correct severity to calculate AER severity Currently the AER severity is calculated by calling cper_severity_to_aer(), but the parameter sent is actually the GHES severity. This causes the AER severity to be incorrect. Fix the parameter to be the CPER severity instead of the GHES severity. Signed-off-by: Tyler Baicar <tbaicar@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Borislav Petkov <bp@suse.de> | 20 September 2016, 19:36:59 UTC |
| 95c3549 | Tyler Baicar | 14 September 2016, 21:14:45 UTC | PCI/AER: Remove duplicate AER severity translation Currently the AER severity is being translated twice in the code flow for PCIe errors. It is first translated in ghes_do_proc() before calling into the AER driver. Then it is translated again when the AER driver calls cper_print_aer(). This causes the severity that is used in cper_print_aer() to be incorrect. Remove the second translation that is in cper_print_aer() since this function is already receiving the correct AER severity. Signed-off-by: Tyler Baicar <tbaicar@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Borislav Petkov <bp@suse.de> | 20 September 2016, 19:35:59 UTC |
| ee6ee49 | Keith Busch | 04 August 2016, 22:09:09 UTC | x86/PCI: VMD: Synchronize with RCU freeing MSI IRQ descs Fix a potential race when disabling MSI/MSI-X on a VMD domain device. If the VMD interrupt service is running, it may see a disabled IRQ. We can synchronize RCU just before freeing the MSI descriptor. This is safe since the irq_desc lock isn't held, and the descriptor is valid even though it is disabled. After vmd_msi_free(), though, the handler is reinitialized to handle_bad_irq(), so we can't let the VMD ISR's list iteration see the disabled IRQ after this. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by Jon Derrick: <jonathan.derrick@intel.com> | 19 September 2016, 18:14:05 UTC |
| b318222 | Jon Derrick | 02 September 2016, 17:53:05 UTC | x86/PCI: VMD: Eliminate index member from IRQ list Use math to discover the IRQ list index number relative to the IRQ list head. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Keith Busch <keith.busch@intel.com> | 19 September 2016, 18:14:05 UTC |
| 53db86a | Jon Derrick | 02 September 2016, 17:53:04 UTC | x86/PCI: VMD: Eliminate vmd_vector member from list type Eliminate unused vmd and vector members from vmd_irq_list and discover the vector using pci_irq_vector(). Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Keith Busch <keith.busch@intel.com> | 19 September 2016, 18:14:05 UTC |
| 75de9b4 | Jon Derrick | 29 August 2016, 17:19:02 UTC | x86/PCI: VMD: Convert to use pci_alloc_irq_vectors() API Convert to use the pci_alloc_irq_vectors() API. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com> | 19 September 2016, 18:14:05 UTC |
| c68db51 | Jon Derrick | 29 August 2016, 17:19:01 UTC | x86/PCI: VMD: Allocate IRQ lists with correct MSI-X count To reduce the amount of memory required for IRQ lists, only allocate their space after calling pci_msix_enable_range() which may reduce the number of MSI-X vectors allocated. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com> | 19 September 2016, 18:14:05 UTC |
| b58ddf1 | Niklas Cassel | 09 September 2016, 07:45:30 UTC | PCI: artpec6: Drop __init from artpec6_add_pcie_port() artpec6_add_pcie_port() is called from artpec6_pcie_probe(), which is not marked __init. It is wrong to call an __init function from a non-__init one, so remove __init from artpec6_add_pcie_port(). [bhelgaas: changelog] Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 14 September 2016, 21:20:47 UTC |
| f7bc638 | Sergei Shtylyov | 08 September 2016, 22:26:18 UTC | PCI: rcar: Fix some checkpatch warnings The R-Car PCIe driver causes 13 warnings from scripts/checkpatch.pl -- let's fix at least 10 easier ones: - line over 80 characters; - blank line missing after declarations; - statements not starting on a tabstop. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> | 14 September 2016, 21:16:34 UTC |
| e3123c2 | Grigory Kletsko | 08 September 2016, 19:32:59 UTC | PCI: rcar: Add multi-MSI support Implement the MSI .setup_irqs() method which enables allocation of several MSIs at once. [Sergei Shtylyov: removed unrelated/unneeded changes, fixed too long lines, reordered the variable declarations, reworded the summary/description.] Signed-off-by: Grigory Kletsko <grigory.kletsko@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> | 14 September 2016, 21:13:58 UTC |
| 7ece141 | Bjorn Helgaas | 06 September 2016, 21:24:37 UTC | PCI/AER: Remove aerdriver.forceload kernel parameter Per the PCI Firmware spec, r3.0, sec 4.5.1, on ACPI systems, the OS must not use AER unless _OSC is present and _OSC grants AER control to the OS. The aerdriver.forceload kernel parameter was a way to enable Linux AER support on ACPI systems that lack _OSC or fail to grant control the the OS. Enabling Linux AER support when the firmware doesn't want us to is a recipe for problems, e.g., the firmware might be handling AER itself. Remove the aerdriver.forceload kernel parameter and related supporting code. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 14 September 2016, 20:27:49 UTC |
| 9ff25e6 | Bjorn Helgaas | 06 September 2016, 21:09:19 UTC | PCI/AER: Remove aerdriver.nosourceid kernel parameter The aerdriver.nosourceid kernel parameter was intended for working around broken chipsets don't supply the source ID for AER events. We recently added PCI_BUS_FLAGS_NO_AERSID, which can be set by quirks for the same purpose. Remove the aerdriver.nosourceid kernel parameter. For anything other than debugging, asking users to find and use kernel parameters is a poor user experience. Instead, we should add PCI_BUS_FLAGS_NO_AERSID quirks for any hardware that needs it. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 14 September 2016, 20:27:38 UTC |
| 29a654e | Bjorn Helgaas | 07 September 2016, 22:50:30 UTC | PCI: pciehp: Remove useless pciehp_get_latch_status() calls Long ago, we updated a "switch_save" field based on the latch status. But switch_save was unused, and ed6cbcf2ac70 ("[PATCH] pciehp: miscellaneous cleanups") removed it. We no longer use the latch status, so remove calls to pciehp_get_latch_status(). No functional change intended. Tested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> | 14 September 2016, 19:25:05 UTC |
| 6e49b30 | Bjorn Helgaas | 08 September 2016, 20:19:58 UTC | PCI: pciehp: Clean up dmesg "Slot(%s)" messages Print slot name consistently as "Slot(%s)". I don't know whether that's ideal, but we can at least do it the same way all the time. No functional change intended. Tested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> | 14 September 2016, 19:25:00 UTC |
| 4947793 | Bjorn Helgaas | 08 September 2016, 20:15:24 UTC | PCI: pciehp: Remove unnecessary guard In pcie_isr(), we return early if no status bits other than PCI_EXP_SLTSTA_CC are set. This was introduced by dbd79aed1aea ("pciehp: fix NULL dereference in interrupt handler"), but it is no longer necessary because all the subsequent pcie_isr() code is already predicated on a status bit being set. Remove the unnecessary test for ~PCI_EXP_SLTSTA_CC. No functional change intended. Tested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> | 14 September 2016, 19:24:54 UTC |
| 69bd3c5 | Mayurkumar Patel | 23 August 2016, 08:58:51 UTC | PCI: pciehp: Don't re-read Slot Status when handling surprise event Previously we read Slot Status when handling a surprise event. But Slot Status might have changed since we identified the event, and the event_type already tells us whether to enable or disable the slot, so there's no need to read it again. Remove handle_surprise_event() and queue the power work directly. [bhelgaas: changelog] Tested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Mayurkumar Patel <mayurkumar.patel@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Rajat Jain <rajatxjain@gmail.com> | 14 September 2016, 19:24:45 UTC |
| 0c923d1 | Mayurkumar Patel | 09 September 2016, 14:10:17 UTC | PCI: pciehp: Don't re-read Slot Status when queuing hotplug event Previously we read Slot Status to learn about hotplug events, then cleared the events, then re-read Slot Status to find out what happened. But Slot Status might have changed before the second read. Capture the Slot Status once before clearing the events. Also capture the Link Status if we had a link status change. [bhelgaas: changelog, split to separate patch] Tested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Mayurkumar Patel <mayurkumar.patel@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> | 14 September 2016, 19:24:40 UTC |
| fad214b | Mayurkumar Patel | 08 September 2016, 20:07:56 UTC | PCI: pciehp: Process all hotplug events before looking for new ones Previously we accumulated hotplug events, then processed them, essentially like this: events = 0 do { status = read(Slot Status) status &= EVENT_MASK # only look at events events |= status # accumulate events write(Slot Status, events) # clear events } while (status) process events The problem is that as soon as we clear events in Slot Status, the hardware may send notifications for new events, and we lose information about the first events. For example, we might see two Presence Detect Changed events, but lose the fact that the slot was temporarily empty: read PCI_EXP_SLTSTA_PDC set, PCI_EXP_SLTSTA_PDS clear # slot empty write PCI_EXP_SLTSTA_PDC # clear PDC event read PCI_EXP_SLTSTA_PDC set, PCI_EXP_SLTSTA_PDS set # slot occupied The current code does not process a removal; it only processes the insertion, which fails because we didn't remove the original device. To avoid this problem, read Slot Status once and process all the events before reading it again, like this: do { read events clear events process events } while (events) [bhelgaas: changelog, add external loop around pciehp_isr()] Tested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Mayurkumar Patel <mayurkumar.patel@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> | 14 September 2016, 19:24:31 UTC |
| 70e8b40 | Bjorn Helgaas | 08 September 2016, 21:43:40 UTC | PCI: pciehp: Return IRQ_NONE when we can't read interrupt status After 1469d17dd341 ("PCI: pciehp: Handle invalid data when reading from non-existent devices"), we returned IRQ_HANDLED when we failed to read interrupt status from the bridge. I think it's better to return IRQ_NONE, as we do in other cases where there's no interrupt pending. This will facilitate refactoring the loop in pcie_isr(): we'll be able to call the ISR in a loop as long as it returns IRQ_HANDLED. Return IRQ_NONE if we couldn't read interrupt status. Tested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> | 14 September 2016, 19:24:25 UTC |
| 9413d96 | Bharat Kumar Gogada | 01 September 2016, 10:14:46 UTC | microblaze/PCI: Add multidomain support for procfs We create a procfs directory for every PCI bus. Previously, the directory name was just the bus number, so using the same bus number in different domains caused a kernel crash when we tried to create a duplicate directory. Make pci_proc_domain() return the domain number, so procfs directories for buses in domain 0 are named with just the bus number, and directories for buses in other domains include both the domain number and the bus number. [bhelgaas: changelog] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com> | 13 September 2016, 15:41:48 UTC |
| b328f3c | Bharat Kumar Gogada | 01 September 2016, 10:14:44 UTC | PCI: xilinx: Dispose of MSI virtual IRQ Dispose of virtual IRQ being created for MSI interrupts. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com> | 13 September 2016, 15:40:02 UTC |
| 8a4036e | Bharat Kumar Gogada | 01 September 2016, 10:14:43 UTC | PCI: xilinx: Clear correct MSI set bit Kernel provides virtual IRQ number at teardown. Get hwirq number from virtual IRQ and clear correct MSI set bit. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com> | 13 September 2016, 15:39:21 UTC |
| 3cd049a | Bharat Kumar Gogada | 01 September 2016, 10:14:42 UTC | PCI: xilinx: Clear interrupt register for invalid interrupt The interrupt decode register is not being cleared if an invalid interrupt arises. Clear the decode register in this case. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com> | 13 September 2016, 15:38:19 UTC |
| b584fa1 | Bharat Kumar Gogada | 01 September 2016, 10:14:41 UTC | PCI: xilinx: Keep both legacy and MSI interrupt domain references When built with MSI support, the legacy domain reference was being overwritten with MSI. Create two separate domains for MSI and legacy interrupts. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com> | 13 September 2016, 15:21:36 UTC |
| f665bd1 | Bharat Kumar Gogada | 30 August 2016, 10:39:17 UTC | PCI: xilinx-nwl: Enable all MSI interrupts using MSI mask The current mask enables and allows only one MSI interrupt on each MSI line. Enable all MSI interrupts, which will also support Endpoints with multi-MSI support. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 13 September 2016, 15:15:41 UTC |
| c2a7ff1 | Bharat Kumar Gogada | 30 August 2016, 10:39:16 UTC | PCI: xilinx-nwl: Expand error logging The current driver logs PCIe core errors. Add logging for individual core events. [bhelgaas: changelog] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 13 September 2016, 14:17:08 UTC |
| 3d664b0 | Geert Uytterhoeven | 31 August 2016, 09:28:22 UTC | PCI: rcar: Don't disable/unprepare clocks on prepare/enable failure If clk_prepare_enable() fails, we must not call clk_disable_unprepare() in the error path. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 12 September 2016, 22:15:09 UTC |
| 6c8b120 | Bjorn Helgaas | 22 August 2016, 19:12:11 UTC | PCI: altera: Remove redundant platform_get_resource() return value check devm_ioremap_resource() fails gracefully when given a NULL resource pointer, so we don't need to check separately for failure from platform_get_resource_byname(). Remove the redundant check. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 12 September 2016, 21:54:17 UTC |
| ce4f1c7 | Ley Foon Tan | 26 August 2016, 01:47:25 UTC | PCI: altera: Move retrain from fixup to altera_pcie_host_init() Previously we used a PCI early fixup to initiate a link retrain on Altera devices. But Altera PCIe IP can be configured as either a Root Port or an Endpoint, and they might have same vendor ID, so the fixup would be run for both. We only want to initiate a link retrain for Altera Root Port devices, not for Endpoints, so move the link retrain functionality from the fixup to altera_pcie_host_init(). [bhelgaas: changelog] Signed-off-by: Ley Foon Tan <lftan@altera.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 12 September 2016, 21:49:13 UTC |
| 8e7ca8c | Po Liu | 29 August 2016, 07:26:58 UTC | PCI: xilinx: Relax device number checking to allow SR-IOV Previously we only allowed device 0 to be directly attached to the root port. But SR-IOV devices may use non-zero device numbers for VFs. Remove the restriction that only device 0 may be attached to a root port. [bhelgaas: changelog] Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 12 September 2016, 21:40:34 UTC |
| e18934b | Po Liu | 29 August 2016, 07:26:58 UTC | PCI: designware: Relax device number checking to allow SR-IOV Previously we only allowed device 0 to be directly attached to the root port. But SR-IOV devices may use non-zero device numbers for VFs. Remove the restriction that only device 0 may be attached to a root port. [bhelgaas: changelog] Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> | 12 September 2016, 21:39:20 UTC |
| d99e30b | Po Liu | 29 August 2016, 07:26:58 UTC | PCI: altera: Relax device number checking to allow SR-IOV Previously we only allowed device 0 to be directly attached to the root port. But SR-IOV devices may use non-zero device numbers for VFs. Remove the restriction that only device 0 may be attached to a root port. [bhelgaas: changelog] Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ley Foon Tan <lftan@altera.com> | 12 September 2016, 21:32:36 UTC |
| 156c553 | Po Liu | 29 August 2016, 07:28:01 UTC | PCI: Check for pci_setup_device() failure in pci_iov_add_virtfn() If pci_setup_device() returns failure, we must return failure from pci_iov_add_virtfn(). If we ignore the failure and continue with an uninitialized pci_dev for virtfn, we crash later when we try to use those uninitialized parts. Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 12 September 2016, 21:23:38 UTC |
| a8499f2 | Bjorn Helgaas | 08 September 2016, 22:30:38 UTC | PCI: pciehp: Rename pcie_isr() locals for clarity Rename "detected" and "intr_loc" to "status" and "events" for clarity. "status" is the value we read from the Slot Status register; "events" is the set of hot-plug events we need to process. No functional change intended. Tested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> | 12 September 2016, 17:26:07 UTC |
| 443b40b | Jon Derrick | 06 September 2016, 19:15:24 UTC | x86/PCI: VMD: Add quirk for AER to ignore source ID VMD root ports change all source ids to the VMD device ID. To find the sender of the AER notification, we need to scan all child devices for the AER sender, rather than relying on the source ID from the message. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 06 September 2016, 19:18:21 UTC |
| 032c3d8 | Jon Derrick | 25 August 2016, 23:26:10 UTC | PCI/AER: Add bus flag to skip source ID matching Allow root port buses to choose to skip source id matching when finding the faulting device. Certain root port devices may return an incorrect source ID and recommend to scan child device registers for AER notifications. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 06 September 2016, 19:15:11 UTC |
| 13f392e | Lorenzo Pieralisi | 15 August 2016, 16:50:46 UTC | PCI: tegra: Fix pci_remap_iospace() failure path On ARM/ARM64 architectures, PCI IO ports are emulated through memory mapped IO, by reserving a chunk of virtual address space starting at PCI_IOBASE and by mapping the PCI host bridges memory address space driving PCI IO cycles to it. PCI host bridge drivers that enable downstream PCI IO cycles map the host bridge memory address responding to PCI IO cycles to the fixed virtual address space through the pci_remap_iospace() API. This means that if the pci_remap_iospace() function fails, the corresponding host bridge PCI IO resource must be considered invalid, in that there is no way for the kernel to actually drive PCI IO transactions if the memory addresses responding to PCI IO cycles cannot be mapped into the CPU virtual address space. The PCI tegra host bridge driver adds the PCI IO resource retrieved from firmware to the host bridge resource windows even if the pci_remap_iospace() call fails; this is an actual bug in that the PCI host bridge would consider the PCI IO resource valid (and possibly assign it to downstream devices) even if the kernel was not able to map the PCI host bridge memory address driving IO cycle to the CPU virtual address space (ie pci_remap_iospace() failures). Add the PCI host bridge driver pci_remap_iospace() failure path and do not add the corresponding PCI host bridge PCI IO resources retrieved through firmware when the pci_remap_iospace() function call fails, fixing the issue. Fixes: e6e9f471f5fe ("PCI: tegra: Use generic pci_remap_iospace() rather than ARM32-specific one") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Thierry Reding <treding@nvidia.com> | 06 September 2016, 17:42:53 UTC |
| 43281ed | Lorenzo Pieralisi | 15 August 2016, 16:50:45 UTC | PCI: generic: Fix pci_remap_iospace() failure path On ARM/ARM64 architectures, PCI IO ports are emulated through memory mapped IO, by reserving a chunk of virtual address space starting at PCI_IOBASE and by mapping the PCI host bridges memory address space driving PCI IO cycles to it. PCI host bridge drivers that enable downstream PCI IO cycles map the host bridge memory address responding to PCI IO cycles to the fixed virtual address space through the pci_remap_iospace() API. This means that if the pci_remap_iospace() function fails, the corresponding host bridge PCI IO resource must be considered invalid, in that there is no way for the kernel to actually drive PCI IO transactions if the memory addresses responding to PCI IO cycles cannot be mapped into the CPU virtual address space. The PCI common host bridge driver does not remove the PCI IO resource from the host bridge resource windows if the pci_remap_iospace() call fails; this is an actual bug in that the PCI host bridge would consider the PCI IO resource valid (and possibly assign it to downstream devices) even if the kernel was not able to map the PCI host bridge memory address driving IO cycle to the CPU virtual address space (ie pci_remap_iospace() failures). Fix the PCI host bridge driver pci_remap_iospace() failure path, by destroying the PCI host bridge PCI IO resources retrieved through firmware when the pci_remap_iospace() function call fails, therefore preventing the kernel from adding the respective PCI IO resource to the list of PCI host bridge valid resources, fixing the issue. Fixes: 4e64dbe226e7 ("PCI: generic: Expose pci_host_common_probe() for use by other drivers") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Will Deacon <will.deacon@arm.com> | 06 September 2016, 17:42:13 UTC |
| 5e8c873 | Lorenzo Pieralisi | 15 August 2016, 16:50:44 UTC | PCI: rcar: Fix pci_remap_iospace() failure path On ARM/ARM64 architectures, PCI IO ports are emulated through memory mapped IO, by reserving a chunk of virtual address space starting at PCI_IOBASE and by mapping the PCI host bridges memory address space driving PCI IO cycles to it. PCI host bridge drivers that enable downstream PCI IO cycles map the host bridge memory address responding to PCI IO cycles to the fixed virtual address space through the pci_remap_iospace() API. This means that if the pci_remap_iospace() function fails, the corresponding host bridge PCI IO resource must be considered invalid, in that there is no way for the kernel to actually drive PCI IO transactions if the memory addresses responding to PCI IO cycles cannot be mapped into the CPU virtual address space. The PCI rcar host bridge driver does not remove the PCI IO resource from the host bridge resource windows if the pci_remap_iospace() call fails; this is an actual bug in that the PCI host bridge would consider the PCI IO resource valid (and possibly assign it to downstream devices) even if the kernel was not able to map the PCI host bridge memory address driving IO cycle to the CPU virtual address space (ie pci_remap_iospace() failures). Fix the PCI host bridge driver pci_remap_iospace() failure path, by destroying the PCI host bridge PCI IO resources retrieved through firmware when the pci_remap_iospace() function call fails, therefore preventing the kernel from adding the respective PCI IO resource to the list of PCI host bridge valid resources, fixing the issue. Fixes: 5d2917d469fa ("PCI: rcar: Convert to DT resource parsing API") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Phil Edworthy <phil.edworthy@renesas.com> CC: Simon Horman <horms+renesas@verge.net.au> | 06 September 2016, 17:41:50 UTC |
| 53f4f7e | Lorenzo Pieralisi | 15 August 2016, 16:50:43 UTC | PCI: versatile: Fix pci_remap_iospace() failure path On ARM/ARM64 architectures, PCI IO ports are emulated through memory mapped IO, by reserving a chunk of virtual address space starting at PCI_IOBASE and by mapping the PCI host bridges memory address space driving PCI IO cycles to it. PCI host bridge drivers that enable downstream PCI IO cycles map the host bridge memory address responding to PCI IO cycles to the fixed virtual address space through the pci_remap_iospace() API. This means that if the pci_remap_iospace() function fails, the corresponding host bridge PCI IO resource must be considered invalid, in that there is no way for the kernel to actually drive PCI IO transactions if the memory addresses responding to PCI IO cycles cannot be mapped into the CPU virtual address space. The PCI versatile host bridge driver does not remove the PCI IO resource from the host bridge resource windows if the pci_remap_iospace() call fails; this is an actual bug in that the PCI host bridge would consider the PCI IO resource valid (and possibly assign it to downstream devices) even if the kernel was not able to map the PCI host bridge memory address driving IO cycle to the CPU virtual address space (ie pci_remap_iospace() failures). Fix the PCI host bridge driver pci_remap_iospace() failure path, by destroying the PCI host bridge PCI IO resources retrieved through firmware when the pci_remap_iospace() function call fails, therefore preventing the kernel from adding the respective PCI IO resource to the list of PCI host bridge valid resources, fixing the issue. Fixes: b7e78170efd4 ("PCI: versatile: Add DT-based ARM Versatile PB PCIe host driver") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Rob Herring <robh@kernel.org> | 06 September 2016, 17:41:15 UTC |
| bcd7b71 | Lorenzo Pieralisi | 15 August 2016, 16:50:42 UTC | PCI: designware: Fix pci_remap_iospace() failure path On ARM/ARM64 architectures, PCI IO ports are emulated through memory mapped IO, by reserving a chunk of virtual address space starting at PCI_IOBASE and by mapping the PCI host bridges memory address space driving PCI IO cycles to it. PCI host bridge drivers that enable downstream PCI IO cycles map the host bridge memory address responding to PCI IO cycles to the fixed virtual address space through the pci_remap_iospace() API. This means that if the pci_remap_iospace() function fails, the corresponding host bridge PCI IO resource must be considered invalid, in that there is no way for the kernel to actually drive PCI IO transactions if the memory addresses responding to PCI IO cycles cannot be mapped into the CPU virtual address space. The PCI designware host bridge driver does not remove the PCI IO resource from the host bridge resource windows if the pci_remap_iospace() call fails; this is an actual bug in that the PCI host bridge would consider the PCI IO resource valid (and possibly assign it to downstream devices) even if the kernel was not able to map the PCI host bridge memory address driving IO cycle to the CPU virtual address space (ie pci_remap_iospace() failures). Fix the PCI host bridge driver pci_remap_iospace() failure path, by destroying the PCI host bridge PCI IO resources retrieved through firmware when the pci_remap_iospace() function call fails, therefore preventing the kernel from adding the respective PCI IO resource to the list of PCI host bridge valid resources, fixing the issue. Fixes: cbce7900598c ("PCI: designware: Make driver arch-agnostic") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Pratyush Anand <pratyush.anand@gmail.com> | 06 September 2016, 17:39:38 UTC |
| db047f8 | Lorenzo Pieralisi | 15 August 2016, 16:50:41 UTC | PCI: aardvark: Fix pci_remap_iospace() failure path On ARM/ARM64 architectures, PCI IO ports are emulated through memory mapped IO, by reserving a chunk of virtual address space starting at PCI_IOBASE and by mapping the PCI host bridge's memory address space driving PCI IO cycles to it. PCI host bridge drivers that enable downstream PCI IO cycles map the host bridge memory address responding to PCI IO cycles to the fixed virtual address space through the pci_remap_iospace() API. This means that if the pci_remap_iospace() function fails, the corresponding host bridge PCI IO resource must be considered invalid, in that there is no way for the kernel to actually drive PCI IO transactions if the memory addresses responding to PCI IO cycles cannot be mapped into the CPU virtual address space. The PCI aardvark host bridge driver does not remove the PCI IO resource from the host bridge resource windows if the pci_remap_iospace() call fails; this is an actual bug in that the PCI host bridge would consider the PCI IO resource valid (and possibly assign it to downstream devices) even if the kernel was not able to map the PCI host bridge memory address driving IO cycle to the CPU virtual address space (ie pci_remap_iospace() failures). Fix the PCI host bridge driver pci_remap_iospace() failure path, by destroying the PCI host bridge PCI IO resources retrieved through firmware when the pci_remap_iospace() function call fails, therefore preventing the kernel from adding the respective PCI IO resource to the list of PCI host bridge valid resources, fixing the issue. Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 06 September 2016, 17:37:55 UTC |
| a5b45b7 | Dexuan Cui | 23 August 2016, 04:49:22 UTC | PCI: hv: Handle hv_pci_generic_compl() error case 'completion_status' is used in some places, e.g., hv_pci_protocol_negotiation(), so we should make sure it's initialized in error case too, though the error is unlikely here. [bhelgaas: fix changelog typo and nearby whitespace] Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: KY Srinivasan <kys@microsoft.com> CC: Jake Oshins <jakeo@microsoft.com> CC: Haiyang Zhang <haiyangz@microsoft.com> CC: Vitaly Kuznetsov <vkuznets@redhat.com> | 06 September 2016, 17:23:30 UTC |
| 665e224 | Dexuan Cui | 23 August 2016, 04:48:11 UTC | PCI: hv: Handle vmbus_sendpacket() failure in hv_compose_msi_msg() Handle vmbus_sendpacket() failure in hv_compose_msi_msg(). I happened to find this when reading the code. I didn't get a real issue however. Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: KY Srinivasan <kys@microsoft.com> CC: Jake Oshins <jakeo@microsoft.com> CC: Haiyang Zhang <haiyangz@microsoft.com> CC: Vitaly Kuznetsov <vkuznets@redhat.com> | 06 September 2016, 17:21:57 UTC |
| 617ceb6 | Dexuan Cui | 23 August 2016, 04:47:23 UTC | PCI: hv: Remove the unused 'wrk' in struct hv_pcibus_device Remove the unused 'wrk' member in struct hv_pcibus_device. Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: KY Srinivasan <kys@microsoft.com> CC: Jake Oshins <jakeo@microsoft.com> CC: Haiyang Zhang <haiyangz@microsoft.com> CC: Vitaly Kuznetsov <vkuznets@redhat.com> | 06 September 2016, 17:21:23 UTC |
| 7d0f8ee | Dexuan Cui | 23 August 2016, 04:46:39 UTC | PCI: hv: Use pci_function_description[0] in struct definitions The 2 structs can use a zero-length array here, because dynamic memory of the correct size is allocated in hv_pci_devices_present() and we don't need this extra element. No functional change. Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: KY Srinivasan <kys@microsoft.com> CC: Jake Oshins <jakeo@microsoft.com> CC: Haiyang Zhang <haiyangz@microsoft.com> CC: Vitaly Kuznetsov <vkuznets@redhat.com> | 06 September 2016, 17:20:44 UTC |
| 0c6045d | Dexuan Cui | 23 August 2016, 04:45:51 UTC | PCI: hv: Use zero-length array in struct pci_packet Use zero-length array in struct pci_packet and rename struct pci_message's field "message_type" to "type". This makes the code more readable. No functionality change. Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: KY Srinivasan <kys@microsoft.com> CC: Jake Oshins <jakeo@microsoft.com> CC: Haiyang Zhang <haiyangz@microsoft.com> CC: Vitaly Kuznetsov <vkuznets@redhat.com> | 06 September 2016, 17:15:46 UTC |
| f8430ea | Joao Pinto | 09 August 2016, 15:49:37 UTC | PCI/MSI: Enable PCI_MSI_IRQ_DOMAIN support for ARC Add ARC as an arch that supports PCI_MSI_IRQ_DOMAIN and add generation of msi.h in the ARC arch. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Vineet Gupta <vgupta@synopsys.com> | 06 September 2016, 15:53:32 UTC |
| e77f847 | Shawn Lin | 03 September 2016, 16:41:09 UTC | PCI: rockchip: Add Rockchip PCIe controller support Add support for the Rockchip PCIe controller found on RK3399 SoC platform. [bhelgaas: fold in Brian's rockchip_pcie_client_irq_handler() OR fix, other fixes and cleanups from Guenter Roeck <linux@roeck-us.net> and me, uninitialized variable fix from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> | 03 September 2016, 16:41:09 UTC |
| d5b0dc8 | Shawn Lin | 04 August 2016, 07:52:07 UTC | dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe controller Add a binding that describes the Rockchip PCIe controller found on Rockchip SoCs PCIe interface. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Rob Herring <robh@kernel.org> | 01 September 2016, 16:29:17 UTC |
| 9e18ad9 | Bjorn Helgaas | 01 September 2016, 14:04:55 UTC | Merge branch 'pci/ptm' into next * pci/ptm: PCI: Add PTM clock granularity information PCI: Add pci_enable_ptm() for drivers to enable PTM on endpoints PCI: Add Precision Time Measurement (PTM) support | 01 September 2016, 14:04:55 UTC |
| a4589a6 | Bjorn Helgaas | 01 September 2016, 14:04:28 UTC | Merge branch 'pci/demodularize' into next * pci/demodularize: PCI: pciehp: Make explicitly non-modular PCI: hotplug: Make core explicitly non-modular PCI: xilinx-nwl: Make explicitly non-modular PCI: xilinx: Make explicitly non-modular PCI: qcom: Make explicitly non-modular PCI: dra7xx: Make explicitly non-modular PCI/AER: Make explicitly non-modular PCI/PME: Make explicitly non-modular PCI: Make DPC explicitly non-modular PCI: generic: Make explicitly non-modular PCI: exynos: Make explicitly non-modular PCI: designware: Make explicitly non-modular PCI: spear: Make explicitly non-modular PCI: portdrv: Make explicitly non-modular PCI: imx6: Make explicitly non-modular PCI: altera: Make explicitly non-modular PCI: altera: Make MSI explicitly non-modular | 01 September 2016, 14:04:28 UTC |
| 31fc0ad | Ley Foon Tan | 26 August 2016, 01:47:24 UTC | PCI: altera: Rework config accessors for use without a struct pci_bus Rework configs accessors so a future patch can use them in _probe() with struct altera_pcie instead of struct pci_bus. Signed-off-by: Ley Foon Tan <lftan@altera.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 26 August 2016, 19:18:59 UTC |
| 8b2ec31 | Bjorn Helgaas | 12 June 2016, 21:26:40 UTC | PCI: Add PTM clock granularity information The PTM Control register (PCIe r3.1, sec 7.32.3) contains an Effective Granularity field: This provides information relating to the expected accuracy of the PTM clock, but does not otherwise affect the PTM mechanism. Set the Effective Granularity based on the PTM Root and any intervening PTM Time Sources. This does not set Effective Granularity for Root Complex Integrated Endpoints because I don't know how to figure out clock granularity for them. The spec says: ... system software must set [Effective Granularity] to the value reported in the Local Clock Granularity field by the associated PTM Time Source. but I don't know how to identify the associated PTM Time Source. Normally it's the upstream bridge, but an integrated endpoint has no upstream bridge. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 25 August 2016, 13:32:34 UTC |
| 70626d8 | Paul Gortmaker | 24 August 2016, 20:57:52 UTC | PCI: pciehp: Make explicitly non-modular This code is not being built as a module by anyone: obj-$(CONFIG_HOTPLUG_PCI_PCIE) += pciehp.o pciehp-objs := pciehp_core.o \ drivers/pci/pcie/Kconfig:config HOTPLUG_PCI_PCIE drivers/pci/pcie/Kconfig: bool "PCI Express Hotplug driver" Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(), etc., so that when reading the driver there is no doubt it is builtin-only. The information is preserved in comments at the top of the file. Note that for non-modular code, module_init() translates to device_initcall(). One could argue that we should use subsys_initcall() here, but for now we stick with runtime equivalence. We delete module.h but we keep the moduleparam.h include, since we are keeping the module_param() that the file has as-is for now. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Kristen Carlson Accardi <kristen@linux.intel.com> | 24 August 2016, 22:28:56 UTC |
| 57b51b9 | Paul Gortmaker | 24 August 2016, 20:57:51 UTC | PCI: hotplug: Make core explicitly non-modular This code is not being built as a module by anyone: obj-$(CONFIG_HOTPLUG_PCI) += pci_hotplug.o [...] pci_hotplug-objs := pci_hotplug_core.o drivers/pci/hotplug/Kconfig:menuconfig HOTPLUG_PCI drivers/pci/hotplug/Kconfig: bool "Support for PCI Hotplug" Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(), etc., so that when reading the driver there is no doubt it is builtin-only. The information is preserved in comments at the top of the file. Remove orphaned exit function in cpci_hotplug_core.c. Note that for non-modular code, module_init() translates to device_initcall(). One could argue that we should use subsys_initcall() here, but for now we stick with runtime equivalence. We would delete module.h and just keep the moduleparam.h include (since the file does use module_param), but there is a try_module_get and module_put pairing that prevents us from doing that. [bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Scott Murray <scott@spiteful.org> CC: Kristen Carlson Accardi <kristen@linux.intel.com> | 24 August 2016, 22:20:14 UTC |
| ff187e7 | Paul Gortmaker | 24 August 2016, 20:57:50 UTC | PCI: xilinx-nwl: Make explicitly non-modular This code is not being built as a module by anyone: drivers/pci/host/Kconfig:config PCIE_XILINX_NWL drivers/pci/host/Kconfig: bool "NWL PCIe Core" Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(), etc., so that when reading the driver there is no doubt it is builtin-only. The information is preserved in comments at the top of the file. Explicitly disallow driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Delete several functions only used by the remove function. Note that for non-modular code, builtin_platform_driver() uses the same init level priority as module_platform_driver(), so this doesn't change init ordering. [bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com> CC: Marc Zyngier <marc.zyngier@arm.com> CC: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> | 24 August 2016, 22:18:17 UTC |
| da4eafc | Paul Gortmaker | 24 August 2016, 20:57:49 UTC | PCI: xilinx: Make explicitly non-modular This code is not being built as a module by anyone: drivers/pci/host/Kconfig:config PCIE_XILINX drivers/pci/host/Kconfig: bool "Xilinx AXI PCIe host bridge support" Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(), etc., so that when reading the driver there is no doubt it is builtin-only. The information is preserved in comments at the top of the file. Note that for non-modular code, builtin_platform_driver() uses the same init level priority as module_platform_driver(), so this doesn't change init ordering. [bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com> | 24 August 2016, 22:16:32 UTC |
| f9a6660 | Paul Gortmaker | 24 August 2016, 20:57:48 UTC | PCI: qcom: Make explicitly non-modular This code is not being built as a module by anyone: drivers/pci/host/Kconfig:config PCIE_QCOM drivers/pci/host/Kconfig: bool "Qualcomm PCIe controller" Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(), etc., so that when reading the driver there is no doubt it is builtin-only. The information is preserved in comments at the top of the file. Note that for non-modular code, MODULE_DEVICE_TABLE is a no-op and builtin_platform_driver() uses the same init level priority as module_platform_driver(), so this doesn't change init ordering. Explicitly disallow driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. [bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Stanimir Varbanov <svarbanov@mm-sol.com> | 24 August 2016, 22:16:19 UTC |
| d29438d | Paul Gortmaker | 24 August 2016, 20:57:47 UTC | PCI: dra7xx: Make explicitly non-modular This code is not being built as a module by anyone: drivers/pci/host/Kconfig:config PCI_DRA7XX drivers/pci/host/Kconfig: bool "TI DRA7xx PCIe controller" Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(), etc., so that when reading the driver there is no doubt it is builtin-only. The information is preserved in comments at the top of the file. Note that for non-modular code, MODULE_DEVICE_TABLE is a no-op and builtin_platform_driver_probe() uses the same init level priority as module_platform_driver_probe(), so this doesn't change init ordering. Explicitly disallow driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. [bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Kishon Vijay Abraham I <kishon@ti.com> | 24 August 2016, 22:02:05 UTC |
| 8756336 | Paul Gortmaker | 24 August 2016, 20:57:46 UTC | PCI/AER: Make explicitly non-modular This code is not being built as a module by anyone: obj-$(CONFIG_PCIEAER) += aerdriver.o aerdriver-objs := aerdrv_errprint.o aerdrv_core.o aerdrv.o drivers/pci/pcie/aer/Kconfig:config PCIEAER drivers/pci/pcie/aer/Kconfig: bool "Root Port Advanced Error Reporting support" Remove uses of MODULE_DESCRIPTION(), MODULE_AUTHOR(), MODULE_LICENSE(), etc., so that when reading the driver there is no doubt it is builtin-only. The information is preserved in comments at the top of the file. Note that for non-modular code, module_init() translates to device_initcall(). [bhelgaas: changelog] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Tom Long Nguyen <tom.l.nguyen@intel.com> | 24 August 2016, 21:59:57 UTC |
| d7def20 | Paul Gortmaker | 24 August 2016, 20:57:45 UTC | PCI/PME: Make explicitly non-modular This code is not being built as a module by anyone: config PCIE_PME def_bool y depends on PCIEPORTBUS && PM Remove traces of modularity so that when reading the driver there is no doubt it is builtin-only. Also delete the .remove function, since that doesn't seem to have a sensible use case. With "normal" endpoint drivers, we have in the past set the suppress_bind_attrs bit to make it clear that the use of ".remove" in a builtin driver was deleted, but here for PCI, it seems overkill to jump through the pcie_port_service_driver and into the struct device_driver in order to finally try and do something similar with the bind setting. Note that for non-modular code, module_init() translates to device_initcall(). Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> | 24 August 2016, 21:56:12 UTC |
