Revision ebff65473f56e6c30de928fd6a4f1ce5ae36e8c5 authored by Shawn Guo on 02 December 2013, 05:26:50 UTC, committed by Mark Brown on 02 December 2013, 11:50:53 UTC
Since devm_card_release() expects parameter 'res' to be a pointer to struct snd_soc_card, devm_snd_soc_register_card() should really pass such a pointer rather than the one to struct device. This bug causes the kernel Oops below with imx-sgtl500 driver when we remove the module. It happens because with 'card' pointing to the wrong structure, card->num_rtd becomes 0 in function soc_remove_dai_links(). Consequently, soc_remove_link_components() and in turn soc_cleanup_codec[platform]_debugfs() will not be called on card removal. It results in that debugfs_card_root is being removed while its child entries debugfs_codec_root and debugfs_platform_root are still there, and thus the kernel Oops. Fix the bug by correcting the parameter 'res' to be the pointer to struct snd_soc_card. $ lsmod Module Size Used by snd_soc_imx_sgtl5000 3506 0 snd_soc_sgtl5000 13677 2 snd_soc_imx_audmux 5324 1 snd_soc_imx_sgtl5000 snd_soc_fsl_ssi 8139 2 imx_pcm_dma 1380 1 snd_soc_fsl_ssi $ rmmod snd_soc_imx_sgtl5000 Unable to handle kernel paging request at virtual address e594025c pgd = be134000 [e594025c] *pgd=00000000 Internal error: Oops: 5 [#1] SMP ARM Modules linked in: snd_soc_imx_sgtl5000(-) snd_soc_sgtl5000 snd_soc_imx_audmux snd_soc_fsl_ssi imx_pcm_dma CPU: 0 PID: 1793 Comm: rmmod Not tainted 3.13.0-rc1 #1570 task: bee28900 ti: bfbec000 task.ti: bfbec000 PC is at debugfs_remove_recursive+0x28/0x154 LR is at snd_soc_unregister_card+0xa0/0xcc pc : [<80252b38>] lr : [<80496ac4>] psr: a0000013 sp : bfbede00 ip : bfbede28 fp : bfbede24 r10: 803281d4 r9 : bfbec000 r8 : 803271ac r7 : bef54440 r6 : 00000004 r5 : bf9a4010 r4 : bf9a4010 r3 : e5940224 r2 : 00000000 r1 : bef54450 r0 : 803271ac Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user Control: 10c53c7d Table: 4e13404a DAC: 00000015 Process rmmod (pid: 1793, stack limit = 0xbfbec240) Stack: (0xbfbede00 to 0xbfbee000) de00: 00000000 bf9a4010 bf9a4010 00000004 bef54440 bec89000 bfbede44 bfbede28 de20: 80496ac4 80252b1c 804a4b60 bfbede60 bf9a4010 00000004 bfbede54 bfbede48 de40: 804a4b74 80496a30 bfbede94 bfbede58 80328728 804a4b6c bfbede94 a0000013 de60: bf1b5800 bef54440 00000002 bf9a4010 7f0169f8 bf9a4044 00000081 8000e9c4 de80: bfbec000 00000000 bfbedeac bfbede98 80328cb0 80328618 7f016000 bf9a4010 dea0: bfbedec4 bfbedeb0 8032561c 80328c84 bf9a4010 7f0169f8 bfbedee4 bfbedec8 dec0: 80325e84 803255a8 bee28900 7f0169f8 00000000 78208d30 bfbedefc bfbedee8 dee0: 80325410 80325dd4 beca8100 7f0169f8 bfbedf14 bfbedf00 803264f8 803253c8 df00: 7f01635c 7f016a3c bfbedf24 bfbedf18 80327098 803264d4 bfbedf34 bfbedf28 df20: 7f016370 80327090 bfbedfa4 bfbedf38 80085ef0 7f016368 bfbedf54 5f646e73 df40: 5f636f73 5f786d69 6c746773 30303035 00000000 78208008 bfbedf84 bfbedf68 df60: 800613b0 80061194 fffffffe 78208d00 7efc2f07 00000081 7f016a3c 00000800 df80: bfbedf84 00000000 00000000 fffffffe 78208d00 7efc2f07 00000000 bfbedfa8 dfa0: 8000e800 80085dcc fffffffe 78208d00 78208d30 00000800 a8c82400 a8c82400 dfc0: fffffffe 78208d00 7efc2f07 00000081 00000002 00000000 78208008 00000800 dfe0: 7efc2e1c 7efc2ba8 76f5ca47 76edec7c 80000010 78208d30 00000000 00000000 Backtrace: [<80252b10>] (debugfs_remove_recursive+0x0/0x154) from [<80496ac4>] (snd_soc_unregister_card+0xa0/0xcc) r8:bec89000 r7:bef54440 r6:00000004 r5:bf9a4010 r4:bf9a4010 r3:00000000 [<80496a24>] (snd_soc_unregister_card+0x0/0xcc) from [<804a4b74>] (devm_card_release+0x14/0x18) r6:00000004 r5:bf9a4010 r4:bfbede60 r3:804a4b60 [<804a4b60>] (devm_card_release+0x0/0x18) from [<80328728>] (release_nodes+0x11c/0x1dc) [<8032860c>] (release_nodes+0x0/0x1dc) from [<80328cb0>] (devres_release_all+0x38/0x54) [<80328c78>] (devres_release_all+0x0/0x54) from [<8032561c>] (__device_release_driver+0x80/0xd4) r4:bf9a4010 r3:7f016000 [<8032559c>] (__device_release_driver+0x0/0xd4) from [<80325e84>] (driver_detach+0xbc/0xc0) r5:7f0169f8 r4:bf9a4010 [<80325dc8>] (driver_detach+0x0/0xc0) from [<80325410>] (bus_remove_driver+0x54/0x98) r6:78208d30 r5:00000000 r4:7f0169f8 r3:bee28900 [<803253bc>] (bus_remove_driver+0x0/0x98) from [<803264f8>] (driver_unregister+0x30/0x50) r4:7f0169f8 r3:beca8100 [<803264c8>] (driver_unregister+0x0/0x50) from [<80327098>] (platform_driver_unregister+0x14/0x18) r4:7f016a3c r3:7f01635c [<80327084>] (platform_driver_unregister+0x0/0x18) from [<7f016370>] (imx_sgtl5000_driver_exit+0x14/0x1c [snd_soc_imx_sgtl5000]) [<7f01635c>] (imx_sgtl5000_driver_exit+0x0/0x1c [snd_soc_imx_sgtl5000]) from [<80085ef0>] (SyS_delete_module+0x130/0x18c) [<80085dc0>] (SyS_delete_module+0x0/0x18c) from [<8000e800>] (ret_fast_syscall+0x0/0x48) r6:7efc2f07 r5:78208d00 r4:fffffffe Code: 889da9f8 e5983020 e3530000 089da9f8 (e5933038) ---[ end trace 825e7e125251a225 ]--- Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mark Brown <broonie@linaro.org>
1 parent 8f1ec93
ak4117.h
#ifndef __SOUND_AK4117_H
#define __SOUND_AK4117_H
/*
* Routines for Asahi Kasei AK4117
* Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define AK4117_REG_PWRDN 0x00 /* power down */
#define AK4117_REG_CLOCK 0x01 /* clock control */
#define AK4117_REG_IO 0x02 /* input/output control */
#define AK4117_REG_INT0_MASK 0x03 /* interrupt0 mask */
#define AK4117_REG_INT1_MASK 0x04 /* interrupt1 mask */
#define AK4117_REG_RCS0 0x05 /* receiver status 0 */
#define AK4117_REG_RCS1 0x06 /* receiver status 1 */
#define AK4117_REG_RCS2 0x07 /* receiver status 2 */
#define AK4117_REG_RXCSB0 0x08 /* RX channel status byte 0 */
#define AK4117_REG_RXCSB1 0x09 /* RX channel status byte 1 */
#define AK4117_REG_RXCSB2 0x0a /* RX channel status byte 2 */
#define AK4117_REG_RXCSB3 0x0b /* RX channel status byte 3 */
#define AK4117_REG_RXCSB4 0x0c /* RX channel status byte 4 */
#define AK4117_REG_Pc0 0x0d /* burst preamble Pc byte 0 */
#define AK4117_REG_Pc1 0x0e /* burst preamble Pc byte 1 */
#define AK4117_REG_Pd0 0x0f /* burst preamble Pd byte 0 */
#define AK4117_REG_Pd1 0x10 /* burst preamble Pd byte 1 */
#define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
#define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
#define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
#define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
#define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
#define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
#define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
#define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
#define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
#define AK4117_REG_QSUB_ABSFRM 0x1a /* Q-subcode absolute frame */
/* sizes */
#define AK4117_REG_RXCSB_SIZE ((AK4117_REG_RXCSB4-AK4117_REG_RXCSB0)+1)
#define AK4117_REG_QSUB_SIZE ((AK4117_REG_QSUB_ABSFRM-AK4117_REG_QSUB_ADDR)+1)
/* AK4117_REG_PWRDN bits */
#define AK4117_EXCT (1<<4) /* 0 = X'tal mode, 1 = external clock mode */
#define AK4117_XTL1 (1<<3) /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
#define AK4117_XTL0 (1<<2) /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
#define AK4117_XTL_11_2896M (0)
#define AK4117_XTL_12_288M AK4117_XTL0
#define AK4117_XTL_24_576M AK4117_XTL1
#define AK4117_XTL_EXT (AK4117_XTL1|AK4117_XTL0)
#define AK4117_PWN (1<<1) /* 0 = power down, 1 = normal operation */
#define AK4117_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */
/* AK4117_REQ_CLOCK bits */
#define AK4117_LP (1<<7) /* 0 = normal mode, 1 = low power mode (Fs up to 48kHz only) */
#define AK4117_PKCS1 (1<<6) /* master clock frequency at PLL mode (when LP == 0) */
#define AK4117_PKCS0 (1<<5)
#define AK4117_PKCS_512fs (0)
#define AK4117_PKCS_256fs AK4117_PKCS0
#define AK4117_PKCS_128fs AK4117_PKCS1
#define AK4117_DIV (1<<4) /* 0 = MCKO == Fs, 1 = MCKO == Fs / 2; X'tal mode only */
#define AK4117_XCKS1 (1<<3) /* master clock frequency at X'tal mode */
#define AK4117_XCKS0 (1<<2)
#define AK4117_XCKS_128fs (0)
#define AK4117_XCKS_256fs AK4117_XCKS0
#define AK4117_XCKS_512fs AK4117_XCKS1
#define AK4117_XCKS_1024fs (AK4117_XCKS1|AK4117_XCKS0)
#define AK4117_CM1 (1<<1) /* MCKO operation mode select */
#define AK4117_CM0 (1<<0)
#define AK4117_CM_PLL (0) /* use RX input as master clock */
#define AK4117_CM_XTAL (AK4117_CM0) /* use X'tal as master clock */
#define AK4117_CM_PLL_XTAL (AK4117_CM1) /* use Rx input but X'tal when PLL loses lock */
#define AK4117_CM_MONITOR (AK4117_CM0|AK4117_CM1) /* use X'tal as master clock, but use PLL for monitoring */
/* AK4117_REG_IO */
#define AK4117_IPS (1<<7) /* Input Recovery Data Select, 0 = RX0, 1 = RX1 */
#define AK4117_UOUTE (1<<6) /* U-bit output enable to UOUT, 0 = disable, 1 = enable */
#define AK4117_CS12 (1<<5) /* channel status select, 0 = channel1, 1 = channel2 */
#define AK4117_EFH2 (1<<4) /* INT0 pin hold count select */
#define AK4117_EFH1 (1<<3)
#define AK4117_EFH_512LRCLK (0)
#define AK4117_EFH_1024LRCLK (AK4117_EFH1)
#define AK4117_EFH_2048LRCLK (AK4117_EFH2)
#define AK4117_EFH_4096LRCLK (AK4117_EFH1|AK4117_EFH2)
#define AK4117_DIF2 (1<<2) /* audio data format control */
#define AK4117_DIF1 (1<<1)
#define AK4117_DIF0 (1<<0)
#define AK4117_DIF_16R (0) /* STDO: 16-bit, right justified */
#define AK4117_DIF_18R (AK4117_DIF0) /* STDO: 18-bit, right justified */
#define AK4117_DIF_20R (AK4117_DIF1) /* STDO: 20-bit, right justified */
#define AK4117_DIF_24R (AK4117_DIF1|AK4117_DIF0) /* STDO: 24-bit, right justified */
#define AK4117_DIF_24L (AK4117_DIF2) /* STDO: 24-bit, left justified */
#define AK4117_DIF_24I2S (AK4117_DIF2|AK4117_DIF0) /* STDO: I2S */
/* AK4117_REG_INT0_MASK & AK4117_REG_INT1_MASK */
#define AK4117_MULK (1<<7) /* mask enable for UNLOCK bit */
#define AK4117_MPAR (1<<6) /* mask enable for PAR bit */
#define AK4117_MAUTO (1<<5) /* mask enable for AUTO bit */
#define AK4117_MV (1<<4) /* mask enable for V bit */
#define AK4117_MAUD (1<<3) /* mask enable for AUDION bit */
#define AK4117_MSTC (1<<2) /* mask enable for STC bit */
#define AK4117_MCIT (1<<1) /* mask enable for CINT bit */
#define AK4117_MQIT (1<<0) /* mask enable for QINT bit */
/* AK4117_REG_RCS0 */
#define AK4117_UNLCK (1<<7) /* PLL lock status, 0 = lock, 1 = unlock */
#define AK4117_PAR (1<<6) /* parity error or biphase error status, 0 = no error, 1 = error */
#define AK4117_AUTO (1<<5) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
#define AK4117_V (1<<4) /* Validity bit, 0 = valid, 1 = invalid */
#define AK4117_AUDION (1<<3) /* audio bit output, 0 = audio, 1 = non-audio */
#define AK4117_STC (1<<2) /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */
#define AK4117_CINT (1<<1) /* channel status buffer interrupt, 0 = no change, 1 = change */
#define AK4117_QINT (1<<0) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
/* AK4117_REG_RCS1 */
#define AK4117_DTSCD (1<<6) /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */
#define AK4117_NPCM (1<<5) /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */
#define AK4117_PEM (1<<4) /* Pre-emphasis detect, 0 = OFF, 1 = ON */
#define AK4117_FS3 (1<<3) /* sampling frequency detection */
#define AK4117_FS2 (1<<2)
#define AK4117_FS1 (1<<1)
#define AK4117_FS0 (1<<0)
#define AK4117_FS_44100HZ (0)
#define AK4117_FS_48000HZ (AK4117_FS1)
#define AK4117_FS_32000HZ (AK4117_FS1|AK4117_FS0)
#define AK4117_FS_88200HZ (AK4117_FS3)
#define AK4117_FS_96000HZ (AK4117_FS3|AK4117_FS1)
#define AK4117_FS_176400HZ (AK4117_FS3|AK4117_FS2)
#define AK4117_FS_192000HZ (AK4117_FS3|AK4117_FS2|AK4117_FS1)
/* AK4117_REG_RCS2 */
#define AK4117_CCRC (1<<1) /* CRC for channel status, 0 = no error, 1 = error */
#define AK4117_QCRC (1<<0) /* CRC for Q-subcode, 0 = no error, 1 = error */
/* flags for snd_ak4117_check_rate_and_errors() */
#define AK4117_CHECK_NO_STAT (1<<0) /* no statistics */
#define AK4117_CHECK_NO_RATE (1<<1) /* no rate check */
#define AK4117_CONTROLS 13
typedef void (ak4117_write_t)(void *private_data, unsigned char addr, unsigned char data);
typedef unsigned char (ak4117_read_t)(void *private_data, unsigned char addr);
struct ak4117 {
struct snd_card *card;
ak4117_write_t * write;
ak4117_read_t * read;
void * private_data;
unsigned int init: 1;
spinlock_t lock;
unsigned char regmap[5];
struct snd_kcontrol *kctls[AK4117_CONTROLS];
struct snd_pcm_substream *substream;
unsigned long parity_errors;
unsigned long v_bit_errors;
unsigned long qcrc_errors;
unsigned long ccrc_errors;
unsigned char rcs0;
unsigned char rcs1;
unsigned char rcs2;
struct timer_list timer; /* statistic timer */
void *change_callback_private;
void (*change_callback)(struct ak4117 *ak4117, unsigned char c0, unsigned char c1);
};
int snd_ak4117_create(struct snd_card *card, ak4117_read_t *read, ak4117_write_t *write,
const unsigned char pgm[5], void *private_data, struct ak4117 **r_ak4117);
void snd_ak4117_reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char mask, unsigned char val);
void snd_ak4117_reinit(struct ak4117 *ak4117);
int snd_ak4117_build(struct ak4117 *ak4117, struct snd_pcm_substream *capture_substream);
int snd_ak4117_external_rate(struct ak4117 *ak4117);
int snd_ak4117_check_rate_and_errors(struct ak4117 *ak4117, unsigned int flags);
#endif /* __SOUND_AK4117_H */
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