Revision f46d1604ed84e5a4107bae1db7283e3a76d72ace authored by Mattia Dongili on 12 August 2007, 07:20:26 UTC, committed by Len Brown on 24 August 2007, 04:56:59 UTC
Signed-off-by: Mattia Dongili <malattia@linux.it> Signed-off-by: Len Brown <len.brown@intel.com>
1 parent b377fd3
cache.h
/*
* include/asm-xtensa/cache.h
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* (C) 2001 - 2005 Tensilica Inc.
*/
#ifndef _XTENSA_CACHE_H
#define _XTENSA_CACHE_H
#include <asm/variant/core.h>
#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
#endif /* _XTENSA_CACHE_H */
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